We aren't sure of your layout and noise levels but normally low current drawing shared grounds are no issue.
There are several methods of ZCS pulses depending on pulse width desired and function.
Even if the pulse is being used for edge trigger or as level duration reset and is a very narrow pulse it may not matter if the pulse leading edge is before and after the actual zero crossing or begins at the zero crossing for a defined period as long. I trust you know the difference. Most uses make no distinction.
For a ZCS signal centered on the zero crossing a separate FW bridge and a low comparator threshold will provide the pulse with the threshold top peak signal level which determines the pulse width.
For example on direct line operated circuits, one can get xx
us duration signals using a large series R with a FW diode bridge and diode clamp to Vcc with the clipped full wave line signal
-adding hysteresis gives some immunity with a controlled % of positive feedback to threshold. We add an RC filter LPF with known phase shift before the FW bridge to improve transient impulse noise rejection greatly. This could mean a common high V1 may be used for both powering and detection with separate bridges.
Another method uses and RC filter on line signal, then rectifies and HPF differentiation to a comparator with hysteresis may also be considered.
Another method simply ac couples the line voltage in a R divider to make a logic square wave then using an RC LPF filter on one side of an XOR gate controls the pulse width after ZCS detection.
This is my preferred method as it offers high SNR, ease of filtering, limiting , precise PW control and uses standard logic gates.
Of course you may not care about false ZCS pulse signals, but I did, so I used impulse LPF rejection, CM ferrite beads and twisted pair wires to offer the highest SNR.
As I recall, I did something like this.
http://goo.gl/DMj2yz