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XST: Problem with simple logical operators

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grubby23

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Hi,

I have a very simple operator problem in VHDL. I try to compare some inputs with logical operators but get an error message...

entity test is
port (
paddr : in std_logic_vector(15 downto 0);
psel : in std_logic;
penable : in std_logic;
pwrite : in std_logic
);
end entity test;

signal wrfifo_full : std_logic;

process (paddr, psel, penable, pwrite, wrfifo_full) is
begin
if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then
dt_fifo_wr_i <= '1';
else
dt_fifo_wr_i <= '0';
end if;

end process;

Unfortuantely, I get then the following error message:

if (((paddr(8 downto 2) = "1000000")) and (psel and penable) and (pwrite and not(wrfifo_full))) then | ncvhdl_p: *E,OPTYMM (hdl/vhdl/test.vhd,523|43): operator argument type mismatch 87[4.3.3.2] 93[4.3.2.2] [7.2]

Anyway sees the problem?

Cheers
 

Hello,

It's better to do the comparison as follows:

Code:
signal wrfifo_full : std_logic;
signal wrfifo_write_allowed : std_logic;  

...

wrfifo_write_allowed <= psel AND penable AND pwrite AND NOT(wrfifo_full); 

...

process (paddr, wrfifo_write_allowed) is
begin
if (((paddr(8 downto 2) = "1000000")) and (wrfifo_write_allowed = '1') ) then
dt_fifo_wr_i <= '1';
else
dt_fifo_wr_i <= '0';
end if;

end process;
 

THat makes so much more sense, thank you very much for your help!
 

To explain the problem properly:

an "if-then-else" tree requires all comparisons to result in a boolen. For you, you tried to "and" together a boolean : (paddr(8 downto 2) = "1000000") with std_logics (psel, pwrite etc). Unless you write a custom "and" function to do this (that also outputs a boolean), it cannot check the if statement. This is why the error was "operator type missmatch".
 

Thats true but only prior to VHDL2k8. In VHDL2k8 you can write explicitly with "??" operator in the if expression.
 

True. But you'll be hard pressed to find software that supports it currently
 

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