[XST] Local clock instead of Global clock

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raka200

Member level 2
bufg clock delay

Hello everybody,

I 'm working on a project with a spartan-3A DSP and I'm using ISE 10.1.03.
I have a clock which drive a shift register and a counter.
I do not want to use a BUFG for this clock, even if I have some spare BUFGs...
(In fact, the input pad of the clock is far away from the BUFGs, and it took to much time to go from the input pad to the BUFG...)
Unfortunately, the mapper and the placer put this clock into a BUFG...
Does anybody know if there is a special constraint that I have to use, or not to use in the UCF ?

I constraint my clock with the PERIOD constraint. Does it force the placement of the clock into a BUFG ?

Thanks !

yanzixuan

Member level 3
clock counter bufg

raka200 said:
Hello everybody,

I 'm working on a project with a spartan-3A DSP and I'm using ISE 10.1.03.
I have a clock which drive a shift register and a counter.
I do not want to use a BUFG for this clock, even if I have some spare BUFGs...
(In fact, the input pad of the clock is far away from the BUFGs, and it took to much time to go from the input pad to the BUFG...)
Unfortunately, the mapper and the placer put this clock into a BUFG...
Does anybody know if there is a special constraint that I have to use, or not to use in the UCF ?

I constraint my clock with the PERIOD constraint. Does it force the placement of the clock into a BUFG ?

Thanks !
the global clock should be assigned to BUFG,because BUFG has the max Fan-out coefficient.if not,there will be some Timing problem.

if you want to tranfer singal from one clock domain to another,you should do synchronization。

raka200

Member level 2
spartan 3a max fanout

I still do not want to use a BUFG : The clock input pin is not a dedicated clock pin. It is physically far away from the BUFGs, and the route delay between the 2 locations is too important for my application (I have to react to a clock edge in 10ns, and there is 5ns of route delay between the input pad and the BUFG). I can't modify the PCB, even it is the best solution.

Moreover, this clock do not drive a lot of FF (<40), and I think I could use this clock as a local clock, the placer/router could cope with it.

But the placer/router still place this clock in a BUFG, even if I didn't instanciate a BUFG primitive. I would like to know how I could force the placer not to use a BUFG.
May be it come from the clock constraint PERIOD in the UCF.

raka200

Member level 2
xst put bufg on clock net

Hello everybody,

I have got the solution from xilinx support :
I have to put
Code:
attribute buffer_type: string;
attribute buffer_type of signal_name: signal is "none";
directly in the code and the synthetizer should not put my net into a BUFG.

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