raka200
Member level 2
bufg clock delay
Hello everybody,
I 'm working on a project with a spartan-3A DSP and I'm using ISE 10.1.03.
I have a clock which drive a shift register and a counter.
I do not want to use a BUFG for this clock, even if I have some spare BUFGs...
(In fact, the input pad of the clock is far away from the BUFGs, and it took to much time to go from the input pad to the BUFG...)
Unfortunately, the mapper and the placer put this clock into a BUFG...
Does anybody know if there is a special constraint that I have to use, or not to use in the UCF ?
I constraint my clock with the PERIOD constraint. Does it force the placement of the clock into a BUFG ?
Thanks !
Hello everybody,
I 'm working on a project with a spartan-3A DSP and I'm using ISE 10.1.03.
I have a clock which drive a shift register and a counter.
I do not want to use a BUFG for this clock, even if I have some spare BUFGs...
(In fact, the input pad of the clock is far away from the BUFGs, and it took to much time to go from the input pad to the BUFG...)
Unfortunately, the mapper and the placer put this clock into a BUFG...
Does anybody know if there is a special constraint that I have to use, or not to use in the UCF ?
I constraint my clock with the PERIOD constraint. Does it force the placement of the clock into a BUFG ?
Thanks !