panos_papajohn
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Design block gets removed during synthesis
Hello,
my design has a ROM memory and a Greatest Common Divisor (GCD) block. With every clock cycle the data set inside the ROM are sent to the GCD block for calculations. I am using a separate VHDL module for connecting the two blocks. During the synthesize phase I receive this warning. Hierarchical block <stage0> is unconnected in block <connectionBlock>. .
Because of this warning I receive a couple of others as result. All the connections to the external signals exist. Is this because I am pre defining output values for the ROM block? Thanks for any help.
CONNECTION BLOCK
ROM BLOCK
GCD BLOCK
Hello,
my design has a ROM memory and a Greatest Common Divisor (GCD) block. With every clock cycle the data set inside the ROM are sent to the GCD block for calculations. I am using a separate VHDL module for connecting the two blocks. During the synthesize phase I receive this warning. Hierarchical block <stage0> is unconnected in block <connectionBlock>. .
Because of this warning I receive a couple of others as result. All the connections to the external signals exist. Is this because I am pre defining output values for the ROM block? Thanks for any help.
CONNECTION BLOCK
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:34:33 04/22/2013
-- Design Name:
-- Module Name: connectionBlock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity connectionBlock is
port(
system_clk: in std_logic;
enable_ROM: in std_logic;
system_reset: in std_logic;
gcd_calculation: out std_logic_vector(13 downto 0);
system_ready: out std_logic;
gcd_ready: out std_logic
);
end connectionBlock;
architecture Behavioral of connectionBlock is
signal start_cal, done_cal: std_logic;
signal input1, input2, gcd_result : std_logic_vector(13 downto 0);
component romBlock port(
clk_in: in std_logic;
enable :in std_logic;
reset: in std_logic;
data: out std_logic_vector(13 downto 0);
ready: out std_logic);
end component;
component gcd port(
clk, reset: in std_logic;
start : in std_logic ;
numberA , numberB: in std_logic_vector (13 downto 0) ;
ready : out std_logic ;
result : out std_logic_vector (13 downto 0));
end component;
begin
stage0: romBlock
port map(system_clk, enable_ROM, system_reset, input2, start_cal);
stage1: gcd
port map(system_clk, system_reset, start_cal, input1, input2, system_ready, gcd_result );
input1<=gcd_result;
gcd_ready<=done_cal;
process(start_cal, gcd_result)
begin
if (start_cal='0') then
gcd_calculation<= gcd_result;
done_cal<='1';
else
gcd_calculation<=(others =>'0');
done_cal<='0';
end if;
end process;
end Behavioral;ROM BLOCK
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:58:41 04/20/2013
-- Design Name:
-- Module Name: romBlock - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity romBlock is
port (
clk_in: in std_logic;
enable :in std_logic;
reset: in std_logic;
data: out std_logic_vector(13 downto 0);
ready: out std_logic);
end romBlock;
architecture Behavioral of romBlock is
signal address: integer range 1 to 100 :=1;
signal data_out: std_logic_vector(13 downto 0);
signal doneReading : std_logic;
begin
process (clk_in, enable)
begin
if (clk_in'EVENT and clk_in='1') then
if (reset='1') then
address <= 1;
else
if(enable='1') then
address<=address+1;
end if;
end if;
end if;
end process;
process (clk_in,reset,data_out,doneReading)
begin
if (clk_in'event and clk_in='1') then
if(reset='1') then
data_out<= "00000000000000";
else
case address is
when 1 => data_out <= "11100101010011";
when 2 => data_out <= "10110111011100";
when 3 => data_out <= "01110111001111";
when 4 => data_out <= "01011011101110";
when 5 => data_out <= "11010010111101";
when 6 => data_out <= "11011100001000";
when 7 => data_out <= "10010010110000";
when 8 => data_out <= "01100100111001";
when 9 => data_out <= "10011011111011";
when 10 => data_out <= "11100101010011";
when 11 => data_out <= "10101110010001";
when 12 => data_out <= "11000000100111";
when 13 => data_out <= "10000000011010";
when 14 => data_out <= "10001001100101";
when 15 => data_out <= "10011011111011";
when 16 => data_out <= "01110111001111";
when 17 => data_out <= "01110111001111";
when 18 => data_out <= "11001001110010";
when 19 => data_out <= "01010010100011";
when 20 => data_out <= "10110111011100";
when 21 => data_out <= "10010010110000";
when 22 => data_out <= "10110111011100";
when 23 => data_out <= "10100101000110";
when 24 => data_out <= "11011100001000";
when 25 => data_out <= "10100101000110";
when 26 => data_out <= "10011011111011";
when 27 => data_out <= "11011100001000";
when 28 => data_out <= "01110111001111";
when 29 => data_out <= "10000000011010";
when 30 => data_out <= "10100101000110";
when 31 => data_out <= "10100101000110";
when 32 => data_out <= "10011011111011";
when 33 => data_out <= "10000000011010";
when 34 => data_out <= "10101110010001";
when 35 => data_out <= "10010010110000";
when 36 => data_out <= "11011100001000";
when 37 => data_out <= "11011100001000";
when 38 => data_out <= "11100101010011";
when 39 => data_out <= "11010010111101";
when 40 => data_out <= "10010010110000";
when 41 => data_out <= "10001001100101";
when 42 => data_out <= "10011011111011";
when 43 => data_out <= "01011011101110";
when 44 => data_out <= "01101110000100";
when 45 => data_out <= "11000000100111";
when 46 => data_out <= "11011100001000";
when 47 => data_out <= "01101110000100";
when 48 => data_out <= "10000000011010";
when 49 => data_out <= "01100100111001";
when 50 => data_out <= "10011011111011";
when 51 => data_out <= "01100100111001";
when 52 => data_out <= "10010010110000";
when 53 => data_out <= "10000000011010";
when 54 => data_out <= "01101110000100";
when 55 => data_out <= "01001001011000";
when 56 => data_out <= "10001001100101";
when 57 => data_out <= "01110111001111";
when 58 => data_out <= "01101110000100";
when 59 => data_out <= "10001001100101";
when 60 => data_out <= "10011011111011";
when 61 => data_out <= "01110111001111";
when 62 => data_out <= "11011100001000";
when 63 => data_out <= "10010010110000";
when 64 => data_out <= "10110111011100";
when 65 => data_out <= "10000000011010";
when 66 => data_out <= "10100101000110";
when 67 => data_out <= "10000000011010";
when 68 => data_out <= "10011011111011";
when 69 => data_out <= "11100101010011";
when 70 => data_out <= "01011011101110";
when 71 => data_out <= "10001001100101";
when 72 => data_out <= "11011100001000";
when 73 => data_out <= "10101110010001";
when 74 => data_out <= "01101110000100";
when 75 => data_out <= "10100101000110";
when 76 => data_out <= "10011011111011";
when 77 => data_out <= "10110111011100";
when 78 => data_out <= "01101110000100";
when 79 => data_out <= "01100100111001";
when 80 => data_out <= "10010010110000";
when 81 => data_out <= "01110111001111";
when 82 => data_out <= "01010010100011";
when 83 => data_out <= "01011011101110";
when 84 => data_out <= "11011100001000";
when 85 => data_out <= "01011011101110";
when 86 => data_out <= "11000000100111";
when 87 => data_out <= "10000000011010";
when 88 => data_out <= "01100100111001";
when 89 => data_out <= "10101110010001";
when 90 => data_out <= "10010010110000";
when 91 => data_out <= "10011011111011";
when 92 => data_out <= "10101110010001";
when 93 => data_out <= "01110111001111";
when 94 => data_out <= "01010010100011";
when 95 => data_out <= "10011011111011";
when 96 => data_out <= "10001001100101";
when 97 => data_out <= "01100100111001";
when 98 => data_out <= "01011011101110";
when 99 => data_out <= "10110111011100";
when 100 => data_out <= "11011100001000";
if(address/=100) then
doneReading<='1';
else
doneReading<='0';
end if;
end case;
end if;
end if;
ready<=doneReading;
data<=data_out;
end process;
end Behavioral;GCD BLOCK
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:26:00 04/22/2013
-- Design Name:
-- Module Name: gcd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity gcd is
port (
clk, reset: in std_logic;
start : in std_logic ;
numberA , numberB: in std_logic_vector (13 downto 0) ;
ready : out std_logic ;
result : out std_logic_vector (13 downto 0)
);
end gcd;
architecture Behavioral of gcd is
type state_type is(idle, swap, sub, res);
signal present_state, next_state :state_type;
signal numberA_reg, numberA_next, numberB_reg, numberB_next: unsigned(13 downto 0);
signal n_reg, n_next: unsigned( 2 downto 0 );
begin
process (clk, reset)
begin
if (reset='1') then
present_state <= idle;
numberA_reg<= (others => '0');
numberB_reg <= (others => '0');
n_reg <= (others => '0');
elsif (clk'event and clk='1') then
present_state<= next_state;
numberA_reg<= numberA_next;
numberB_reg<= numberB_next;
n_reg<= n_next;
end if;
end process;
process(present_state, numberA_reg, numberB_reg,n_reg, start, numberA, numberB, n_next)
begin
numberA_next<= numberA_reg;
numberB_next <= numberB_reg;
n_next<= n_reg;
case present_state is
when idle =>
if start='1' then
numberA_next <= unsigned(numberA);
numberB_next<= unsigned(numberB);
n_next <= (others => '0');
next_state<= swap;
else
next_state<= idle;
end if;
when swap =>
if (numberA_reg=numberB_reg) then
if( n_reg=0) then
next_state<= idle;
else
next_state<= res;
end if;
else
if(numberA_reg(0)='0') then
numberA_next <= '0'&numberA_reg(13 downto 1);
if(numberB_reg(0)='0') then
numberB_next<= '0'&numberB_reg(13 downto 1);
n_next <= n_reg+1;
end if;
next_state<= swap;
else
if(numberB_reg(0)='0') then
numberB_next<= '0'&numberB_reg(13 downto 1);
next_state <=swap;
else
if(numberA_reg< numberB_reg) then
numberA_next <=numberB_reg;
numberB_next<= numberA_reg;
end if;
next_state <=sub;
end if;
end if;
end if;
when sub =>
numberA_next<= numberA_reg - numberB_reg;
next_state <= swap;
when res =>
numberA_next<= numberA_reg(12 downto 0)&'0';
n_next <= n_reg - 1;
if(n_next =0) then
next_state<= idle;
else
next_state<= res;
end if;
end case;
end process;
ready<='1' when present_state=idle else '0';
result<= std_logic_vector(numberA_reg);
end Behavioral;
Last edited:
