XOR to an undefined length word [VHDL]

[eafox]

How can I apply XOR between the bits in a word if I don't know its length beforehand?
For example if the word is 1101 then i want to calculate:

result <= word(3) xor word (2) xor word (1) xor word(0);

In a higher level language probably I would use a loop, but I don't know how to do it in VHDL and if it's synthesizable.

Thanks,

Edson

 

[mrflibble]

So you define the result for the MAXIMUM word size you will have to handle. And then the smaller words you pad with zeros. Problem solved.

And if you don't know the maximum word size either then that's too bad. Then you would have to change the design constraints such that you DO know the maximum, or adopt a streaming approach.

 

[TrickyDicky]

if you're using an older version of the languge, just write a function (or inline inside a process). Loops are perfectly synthesisable if you know what you're doing.:

function xor_array( s : std_logic_vector ) return std_logic is
  variable ret : std_logic := '0';
begin
  for i in s'range loop
    ret := ret xor s(i);
  end loop;

  return ret;
end function;

....

op <= xor_array(input);

or if you're lucky enough to have 2008 support, you can simly write:

op <= xor input;

 

[mrflibble]

Temporal loop != spatial loop. I think what you are referring to is using a loop for unrolling logic (aka spatial loop), while the OP when using the word loop is he means sequential processing (aka temporal loop), since he mentions higher level programming.

At any rate, using the loop construct you would still need to tell your loop what size (s'range in this case). Now that I think about it, you can read the OP in 2 ways. One is that he doesn't know the word size beforehand while designing. And the other (my assumption in previous post) is that he doesn't know the word size at run time. If he meant unknown during design process, but will be fixed before we get to runtime ... I'll shut up because in that case you do what TrickyDicky said.

If he meant word size also not known during runtime, and we have to do a flexible XOR depending on wordsize, then see my previous post. MMmmh, and it's more likely that he means fixed word size, but he just doesn't know exactly what size just yet, since that's a bit more common.

- - - Updated - - -

or if you're lucky enough to have 2008 support, you can simly write:

op <= xor input;

Yeah, I was wondering ... surely VHDL must have an easy bit-wise xor reduction too. I'm only familiar with verilog and there it would be "op <= ^ input;"

In fact, that's so trivial that I assumed that the OP surely must mean runtime. But, shame on me for making an assumption. tsk.

 

[TrickyDicky]

Silly me for forgetting this:

the std_logic_misc library has reduction functions:

op <= xor_reduce(input);

This does exactly what my function did.