sontsont
Newbie level 1
because of the fighting between signals, some tranif in xor gate is rtranif (down strength by 1 level),
so the output strength level is "weak",
and if the output meet the latch circuit (which has "pull" strength),
the xor gate output disappear.
how can I solve this problem?
so the output strength level is "weak",
and if the output meet the latch circuit (which has "pull" strength),
the xor gate output disappear.
how can I solve this problem?
