Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

XMR in Verilog : Use models

Status
Not open for further replies.
A hierarchical reference in Verilog (sometimes called a cross module reference - XMR, cross reference - XREF, or out-of-module reference OOMR) can be thought of as a way of a probing and patching the design for debugging from your testbench without having a signal brought up to the top-level of your design via a network of wires and port connections. When you instantiate modules throughout your design, all signals (wires or variables) are given hierarchical pathnames that you can reference directly. I recommend limited use of these references as it makes your code difficult to follow and maintain as the hierarchy changes.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top