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A hierarchical reference in Verilog (sometimes called a cross module reference - XMR, cross reference - XREF, or out-of-module reference OOMR) can be thought of as a way of a probing and patching the design for debugging from your testbench without having a signal brought up to the top-level of your design via a network of wires and port connections. When you instantiate modules throughout your design, all signals (wires or variables) are given hierarchical pathnames that you can reference directly. I recommend limited use of these references as it makes your code difficult to follow and maintain as the hierarchy changes.