xilinx12.1 problem while working on hardware part (edk) in generating bitstream

[kaoutar3005]

hello i va started working with xilinx12.1 for my fpga but while generating bitstream on the harware part i have some errors that i just can t get red of them:

ERROR:ConstraintSystem:58 - Constraint <NET "*/tx_client_clk*" TNM_NET =
"clk_client_tx0";> [system.ucf(295)]: NET "*/tx_client_clk*" does not match
any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET "*/rx_client_clk*" TNM_NET =
"clk_client_rx0";> [system.ucf(300)]: NET "*/rx_client_clk*" does not match
any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET "*/tx_gmii_mii_clk*" TNM_NET =
"clk_phy_tx0";> [system.ucf(305)]: NET "*/tx_gmii_mii_clk*" does not match
any design objects.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1
please who can help

 

[ads-ee]

This isn't a bitstream generation problem. It's a ngdbuild issue where synthesis has change the name of the clock to something else.

This means the clock names have changed during synthesis and/or translation. I've found this to happen more often when I use cores that are buried in the hierarchy or when the coding of the clock infers the clock buffers. You might what to enable the keep_hierarchy option in the synthesis process properties dialog along with the advanced option netlist_hierarchy set to rebuilt. This will help ensure the hierarchical names are kept and rebuilt in top down flattened compilations (which is the default along with no hierarchy preservation).

You can use the view technology schematic to find the new name if keeping the hierarchy intact doesn't resolve the issue. Other options are are to include synthesis constraints to preserve the name, which I've found to sometimes do unexpected things. I've also specified the hierarchical name to the actual cell output port, which synthesis usually never changes as long as the hierarchy doesn't change.

Regards

 

[kaoutar3005]

tnx a lot for answering,
however i didn t understand the steps that you were describing ..i made some changes but i still have these errors just after that i click on generate bitstream ( when i click on generate netlist no problems are found) :
ERROR:ConstraintSystem:58 - Constraint <NET "*/tx_client_clk*" TNM_NET =
"clk_client_tx0";> [system.ucf(279)]: NET "*/tx_client_clk*" does not match
any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET "*/rx_client_clk*" TNM_NET =
"clk_client_rx0";> [system.ucf(284)]: NET "*/rx_client_clk*" does not match
any design objects.
ERROR:ConstraintSystem:58 - Constraint <NET "*/tx_gmii_mii_clk*" TNM_NET =
"clk_phy_tx0";> [system.ucf(289)]: NET "*/tx_gmii_mii_clk*" does not match
any design objects.
ERROR:Xflow - Program ngdbuild returned error code 2. Aborting flow execution...
make: *** [__xps/system_routed] Error 1

 

[ads-ee]

ngdbuild is spitting out the error so this is after generating the netlist with XST. If you are unaware of the build process in ISE here it is.

XST->ngdbuild->map->par->bitgen

As ngdbuild annotates the synthesized netlist with the UCF file constraints it will be the first time that reports name errors with the signals in the netlist.

Regardless you need to look up how to generate a schematic from the netlist using the view technology schematic under the design tab of the process panel. Open up the Synthesize XST and click on View Technology. You can then search through the entire design to find synthesized names for any design element.

Regards

 

[permute]

These all come from a TEMAC core. You can try to remove these UCF constraints for now (and the related constraints that reference these TNM). From there, you can look at the netlist (fpga editor) and the code (look in the pcores dir in the xilinx install dir, somewhere in EDK IIRC). The PAR report will also list bufg and bufr in the design, along with net names. This should help if retiming/etc... are changing the net names.

It is also possible the UCF file has old constraints that are no longer relevant.