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Xilinx XPower Analyzer Confidence Level

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dayana42200

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Hello everyone.

Im using ISE Design Suite 14.7 and Xilinx XPower Analyzer to find the total power for my design.

1. I notice that both the design nets matched and simulation nets matched is not 100%. Why is that?
2. What can be done to increase the confidence level?
3. One more thing, based on the summary, the quiescent power is higher than the dynamic power. Should the dynamic power is higher than the quiescent power? Can you share your opinion based on your experience?

Thank you.
 

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FvM

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The table shows near to zero logic utilization, respectively no relevant dynamic power. You must know if this is realistic.
 

dayana42200

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@FvM

Thank you for the reply.
Does that mean the design is to small for dynamic power analysis?

What about the quiscent power?
Where would the power come from?
 
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ThisIsNotSam

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@FvM

Thank you for the reply.
Does that mean the design is to small for dynamic power analysis?

What about the quiscent power?
Where would the power come from?

it means your design is not switching, it's not burning dynamic power. it's just sitting there and leaking.
 

dayana42200

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@ThisIsNotSam

I see

Ive generated the SAIF file based on the PAR simulation.
I do notice the PAR simulation doesnt give the same result as the behavioral simulation.

If I attach the .Saif and glbl file (generated from post place & route model) would it helps you to understand what is happening in my design?
It would helpful to me since I really understand what is mentioned in both files.
 
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