minho_ha
Junior Member level 3
Xilinx Virtex-6 PCIe wrapper 1.4 EP synthesis error
I tried to synthesize PCIe wrapper 1.4 (endpoint, EP) given by 'coregen' into Virtex6 (ML605 board).
Then i got below error messages
ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 207: Macro <PIO_RX_ENGINE> is not defined.
ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 253: Macro <PIO_TX_ENGINE> is not defined.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 68: <trn_trem_n> is not a port.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 81: <trn_rrem_n> is not a port.
ERROR:HDLCompiler:598 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 60: Module <PIO_EP> ignored due to previous errors.
There is no change.
When i synthesized rootport (RP), there is no error message. Is there any difference between EP and RP??
I used Xilinx ISE 11.5 and ML605 board.
I tried to synthesize PCIe wrapper 1.4 (endpoint, EP) given by 'coregen' into Virtex6 (ML605 board).
Then i got below error messages
ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 207: Macro <PIO_RX_ENGINE> is not defined.
ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 253: Macro <PIO_TX_ENGINE> is not defined.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 68: <trn_trem_n> is not a port.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 81: <trn_rrem_n> is not a port.
ERROR:HDLCompiler:598 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 60: Module <PIO_EP> ignored due to previous errors.
There is no change.
When i synthesized rootport (RP), there is no error message. Is there any difference between EP and RP??
I used Xilinx ISE 11.5 and ML605 board.