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Xilinx virtex-6 PCIe wrapper 2.5 error

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minho_ha

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Xilinx Virtex-6 PCIe wrapper 1.4 EP synthesis error

I tried to synthesize PCIe wrapper 1.4 (endpoint, EP) given by 'coregen' into Virtex6 (ML605 board).

Then i got below error messages

ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 207: Macro <PIO_RX_ENGINE> is not defined.
ERROR:HDLCompiler:870 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 253: Macro <PIO_TX_ENGINE> is not defined.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 68: <trn_trem_n> is not a port.
ERROR:HDLCompiler:53 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 81: <trn_rrem_n> is not a port.
ERROR:HDLCompiler:598 - "D:\test\test0628_2\v6_pcie_v1_4\example_design\PIO_EP.v" Line 60: Module <PIO_EP> ignored due to previous errors.


There is no change.

When i synthesized rootport (RP), there is no error message. Is there any difference between EP and RP??

I used Xilinx ISE 11.5 and ML605 board.
 

minho_ha

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I posted similar one before. But there are no appropriate answers. So I wanna post it again.

I tried to implement PCIe wrapper v2.5 (target device is virtex 6, ML605 board) given by ISE 14.7.

Trying implementation, in 'map' process, two errors occur.

ERROR:pack:2309 - Too many bonded comps of type "IOB" found to fit this device.
ERROR:Map:237 - The design is too large to fit the device. Please check the Design Summary section to see which resource requirement for
your design exceeds the resources available in the device. Note that the number of slices reported may not be reflected accurately as
their packing might not have been completed.


I did not change the given source codes.

Why does above errors occur?? In 'map report', given IP needs 662 IOBs, but virtex 6 which i used has only 600 IOBs.

Is there anyone who can help me?
 

ads-ee

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I already gave you the most likely cause in your other thread on the same subject. Of course you never responded with any information about that.

BTW, Stop making new threads on this problem.
 

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