Xilinx Virtex 6 Maximum clock frequency of design ?

[vyasa]

I am using Xilinx ISE 12.4 and Virtex6 Lx75t speed grade -3 device. the design shows a maximum clock frequency of 1100 MHz in post-place and route static timing report. Is it possible to achieve this high speed in the virtex6 fpga?

When i do a post PAR simulation at around 800 MHz , the design shows timing errors?
Is the tool not showing proper results?

Please help.


Thanks in Advance.