Xilinx Unsigned parallel squarer design

[akeedthe]

Hi,

I am looking to design a parallel squarer circuit using VHDL and try optimizing interconnections to see if it can be more efiicient.

The design template Im looking to follow is based on this paper:

**broken link removed**

(Parallel squarer design using pre-calculated sums of partial products)

and

https://ieeexplore.ieee.org/xpl/art...yText=Power+and+Area+Efficient+Squarer+Design

(Power and Area Efficient Squarer Design)

How would it be a good way to start off this project please?

I figured that I dont need the partial products themselves as I can input them for the time being to test the circuit. So i presume I would need to start with the full and half adder networks. Also, is the vector merger adder the same as using Carry Look Ahead Logic?

Any opinions on this would be appreciated.

Thanks in advance

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Also, would anyone be knowing the standard VHDL library for the full adder, half adder and carry look ahead adder please and where I can find it?