--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:27:37 03/15/08
-- Design Name:
-- Module Name: InstRom5 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity InstRom5 is
Port ( InstAddress : in std_logic_vector(3 downto 0);
InstOut : out std_logic_vector(3 downto 0));
end InstRom5;
architecture Behavioral of InstRom3 is
type ROM_Array is array (0 to 3)
of std_logic_vector(3 downto 0);
constant Content: ROM_Array := (x"0",
x"1",
x"1",
x"1");
begin
end Behavioral;