Xilinx System Generator Help!!

[Ahmed Ragab]

xilinx system generator

Al-Salamo 3alaikom Everyone,

I'm working with the evaluation version of Xilinx SysGen and was building up a system for simulation.
I need to add a look-up table so I found there is a ROM in the Xilinx blockset.
All it has is an input address bus and a data output bus.

The problem is a can't find a way to access this ROM in order to change the data saved in it's memory locations !!

Could anyone help me solve this problem ?!

It's 32 bits wide and contains 16 locations, so for any combination of my 4 input bits I should get the equivalent 32 bits as an output.

Thanks in advance

Salam.

 

[wadaye]

xilinx system generator examples

Hi Ahmed Ragab,

It's seems you wanna change the content of a ROM, that's impossible for a ROM. If

you wanna do these you have to use RAM or change the initial file for the ROM.

 

[Ahmed Ragab]

xilinx initialize sdram from prom

Thanks alot Wadaye, that's exactly what I need to do, change the initial file of the ROM.
How can that be achieved ?!

 

[echo47]

xilinx rom initialization

Do you want to change the ROM data, or simply initialize the ROM data? As wadaye says, it doesn't make sense to change ROM data, because then it would be a RAM.

To initialize the ROM:
- Add the block to your diagram: Xilinx Blockset -> Memory -> ROM.
- Double-click the new ROM block. A dialog box opens.
- Modify "Initial Value Vector" with with an initialization equation such as sin(pi*(0:15)/16)
- Change "Number of Bits" to 32, and maybe change the other settings as required.

 

[Ahmed Ragab]

system generator sad simulink

Would it be possible to initialize the ROM memory locations by initially "writing" into it a sequence of zeroes and ones which I choose ? instead of writing it as an equation?!

Till now I understand what echo47 has said and I agree I can't "write" to a ROM

So still echo, have you got a solution for this problem ?!

Thanks in advance all.

Salam

 

[echo47]

xilinx rom system generator

You can write a MATLAB expression that initializes the ROM with your pattern of ones and zeros. The expression can also be a simple matrix or a read-data-from-file function such as dlmread. I have put some really long strings into that "Initial Value Vector" field.

The Xilinx ROM block will be implemented in the FPGA as a Block ROM. The FPGA provides no way to write into a Block ROM after it has been initialized, so it seem reasonable that Simulink doesn't give you any way to write to it either.

 

[eldieb147]

formula expression sysgen

you can initialize the ROM by creating a ".coe" file that holds all the words to be written in the ROM.... you can include this file while generating the ROM from the coregen...

The format of the ".coe" should be as follows:

MEMORY_INITIALIZATION_RADIX = (2,16 or 10) ;
MEMORY_INITIALIZATION_VECTOR =

word0 ,
word1,
word2,
.
.
.
wordn ;

 

[r_a_c_a_4_u]

system generator sdr

the problem im facing is the same ... i find no option in simulink/sysgen that will allow me to initialise my ROM with addresses and data corresponding each address .... if its not possible to initialise then how one would simulate the design using ROM ...


and this code

The format of the ".coe" should be as follows:

MEMORY_INITIALIZATION_RADIX = (2,16 or 10) ;
MEMORY_INITIALIZATION_VECTOR =

is for ISE i think ... i need a way to initialise ROM in simulink ...

help needed ....
thnx in advance

 

[kavitha_bonthu]

rom block in system generator

insted of giving the eqation in the block ROm,
you can enter the data in square brackets seperated by ,
Ex:[x,y,z].

 

[r_a_c_a_4_u]

how to initialize data to block rom xilinx

yea kavitha ... i had tried that

you can enter the data in square brackets seperated by ,
Ex:[x,y,z].

but it din work for some unknown reason ... then i had to write a vhdl code and use a black box to get the data corresponding to a given address

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:27:37 03/15/08
-- Design Name:
-- Module Name: InstRom5 - Behavioral
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity InstRom5 is
Port ( InstAddress : in std_logic_vector(3 downto 0);
InstOut : out std_logic_vector(3 downto 0));
end InstRom5;

architecture Behavioral of InstRom3 is
type ROM_Array is array (0 to 3)
of std_logic_vector(3 downto 0);

constant Content: ROM_Array := (x"0",
x"1",
x"1",
x"1");
begin
end Behavioral;

 

[aliumair926]

xilinx memory initial file

Hi,...i am working on System Genetaror to make an AM transmitter and receiver and implement on SFF SDR Development Platform ,...i am facing a lot of problems regarding making my models ,...is there anybody out there to help me

 

[xtcx]

rom ram xilinx system generator

Hi aliumair, I'm either working in Matlab based system generator for SDR Development....But I'm not designin AM or FM, instead only digital modulation, such as ask,fsk,psk,qpsk. My current project is qpsk. I guess we both can share lot more and gain mutually....You could share if you wish, I will let you what I know or have leanrt in sys-gen using simulink.....
Regards.,

 

[heartbeat_0009]

hi
i m also working on system generator. i think we can help each other in this regard.

 

[radhika_c29]

Hello all

I am working on the RAM block , i understand the RAM block working like so,
if i take the data with 20 values and 10 memory locations in address, now i wanted to have the 11th data value to be written to the 10th address and to through out the 1st data value from the 1st memory location out from the RAM.
according to my understanding RAM should do this!!

but now as an output, i get it same as data input but with some delay.
can somebody tell me how to make it work as it should be...

Thanks all