Xilinx synthesis problem

[Zerox100]

Dear my friends,

I have a created a soc project using vivado 2018. I have added an accelerator as an IP to main cpu of soc.
My problem is that when I synthesis the accelerator as a separate project (mode outofcontext) it uses 57000 LUT in synthesis. But when I add it to my design as IP it uses 65000 LUT in synthesis that is more than FPGA resources.
I have analyzed the synthesis details. Each part takes 10-15% more resources. Anybody knows any solution to my problem?

THX

 

[kaz1]

synthesis report on resource usage is preliminary. It is finalised after placement/routing (implementation).
The tool tries to fit and pass timing on chosen fpga and as such may require more resource. You should check you are not over constraining design timing. There are also settings targeting resource optimisation at ip level or project level.

I have tried out-of-context Xilinx technology and as far as I noticed it is synthesis only. Not final placement/routing and I don't see it as New technology as Xilinx claims. It may just shorten tool processing time.

 

[FvM]

10 -15 % looks like normal range to me. There are many possible reasons why the IP takes more resources when implemented in the full design, e.g. datapath muxes, lack of dedicated multipliers, register duplication to keep timing constraints.

 

[Zerox100]

10 -15 % looks like normal range to me. There are many possible reasons why the IP takes more resources when implemented in the full design, e.g. datapath muxes, lack of dedicated multipliers, register duplication to keep timing constraints.

Thank you for your answer
Is there a way reduces the 10-15% to 5-7%?

 

[FvM]

Impossible to tell without analysing the design in detail.