Xilinx synthesis & CLOCK signals

[Mirzaaur]

hi all;

in my design I generate local clock using DCM and provide a clock on output of the virtexII.

when i try to create timing constraints after synthesis using constraints editor, I don't get the clock signals there. but some other signal which are not clock they are listed as clock. I checked these signals are detected for the transition at any level.


HOW I CAN TELL XST - SYNTHESIZER NOT TO USE CERTAIN SIGNALS AS CLOCK?

thankful for any hint or tip.

mirza

 

[vintujose]

Hi instead of using the constraint editor try to have an constraint file if you check the xilinx website on topic of constraints you will find that there are certain command formats to be followed in the constraint file such that you force the file to behave in the way you want it .

hope this helps

 

[cherjier]

i give you an example:
for the input clock "clkin" to the DCM and generate 2 clocks "clkfx" and "clkdv" shown in the diagram below

the constraints that you need to specified only the input clock whereas the XST will generate the clock constraints for clkfx and clkdv which you can find on the XST report.

here the example clock contraints:
NET "clkin" TNM_NET = "clkin";
TIMESPEC "TS_clkin" = PERIOD "clkin" 100.000 ns HIGH 50.00%;