Xilinx synthesis and PNR flow

[beowulf]

Hello all,
I want to understand the synthesis and PNR flow for xilinx families. Is there a single (or maybe a couple) document that describes:

1. Directory structure for the design (rtl/syn/ etc) that is expected by ISE
2. Setting up script files for command line
3. List of files and reports generated by ISE (Very IMP)
4. How to read basic timing reports and their format
5. An example flow

I tried looking through xilinx documentation, but theres so much there that I was lost after a while.

Can a xilinx expert help me put things in the right perspective.

Thanks,
Beo

 

[devas]

Hi,

A starting point:

- Xilinx Synthesis: XST User Guide (UG627)
- Command Line Syntax/Tools: Command Line Tools User Guide (UG628)

Devas

 

[beowulf]

Thanks for the pointers...I and looking at the Command line syntax user guide.
I remember there was a flow diagram that nicely showed what file is generated at which level of the flow. I am trying to find that document.
Also looking for a complete example script with the constraints set.

Thanks
Beo

 

[beowulf]

I was looking for something similar...sorry, its a bit untidy. I guess the prom file is .mcs or something. Please point out if there are any mistakes

 

[devas]

Hi Beowulf,

Your schematic looks fine to me. I do not know the output file of promgen. I have never used it.
I am not aware of a Xilinx document with such a schematic. Even it makes sense for every designer.

Devas

 

[permute]

there's also TRCE and DRC, which mainly generate reports. the DRC report is usually worthless.