Xilinx SP605 PCIe-DDR design problem

[Wild Life]

Hello everybody,

My goal is to connect a PCIe to a DDR3 on Xilinx Spartan-6 SP605 Evaboard wwithout using a DMA: I tried many times but I didn't solved my problems...

I downloaded the SP605 PCIe x1 Gen1 Design Files for Xilinx ISE 12.1 and I got the example design, that reads and writes from/to Block Ram using the LocalLink interface of PCIe, obviously "converted" to a classic ram read_data/read_en-write_data/write_en protocol... the "classic" block ram access signals, if you know what I mean.


I'd like to remove the Block ram and replacing it with a DDR3 interface, using MIG: I didn't understand (and I try many times!!!) how to "adapt" the LocalLink signals (or also the block Ram Signals) to MCB cmd/data interface, without using a DMA



I have the following signals for two port DDR3 interface (p2 is read only, p3 is write only), both 32 bit wide



signal p2_cmd_en, p2_cmd_empty, p2_cmd_full: std_logic;
signal p2_cmd_instr: std_logic_vector(2 downto 0);
signal p2_cmd_bl: std_logic_vector(5 downto 0);
signal p2_cmd_byte_addr: std_logic_vector(29 downto 0);
signal p2_rd_en, p2_rd_full, p2_rd_empty, p2_rd_overflow, p2_rd_error: std_logic;
signal p2_rd_data: std_logic_vector(31 downto 0);



signal p3_cmd_en, p3_cmd_empty, p3_cmd_full: std_logic;
signal p3_cmd_instr: std_logic_vector(2 downto 0);
signal p3_cmd_bl: std_logic_vector(5 downto 0);
signal p3_cmd_byte_addr: std_logic_vector(29 downto 0);
signal p3_wr_en, p3_wr_full, p3_wr_empty, p3_wr_underrun, p3_wr_error: std_logic;
signal p3_wr_data: std_logic_vector(31 downto 0);



Could anybody help me? i also didn't undertsand very well what's the best choice for cmd/data management: What's the order of signal? in the User Guide there's written the command and the data timing but I have to manage before the command ones or the data ones? The two timing patterns are separated in two images so I didn't understand the order I have to manage them.



Coul anybody help me? I tried every way to solve it but nothing helped me... I hope somebody help me!

 

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Do you know what a DMA is? You certainly don't need DMA to do what you want. You might incur latency on the transaction due to having to setup the SDRAM for any reads and writes from PCIe, but that is just a simple FSM and possibly a FIFO to hold data while waiting for the SDRAM to be ready.

All you want is an interface module that translates controls from one bus protocol to another. And performs any control requirements like setting up the bank accesses for the SDRAM before reading/writing data to the SDRAM. What's so difficult about doing that? If you want an interface that doesn't have as many signals you have to deal with then use MIG and produce an AXI interface instead of using the MCB directly.

I get the impression this is for a school project. Makes me wonder what universities teach engineering students these days...

Regards