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Xilinx simulation failed

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T Hima

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Hi,
I have linked the sysgen file as source to my topmodule vhdl code. sysgen file is linked as .ngc extension. On simulating the test bench code it threw errors..."static elaboration of top level VHDL design unit testbench_file_name in library work failed " and "cannot open my_acos1.mif" and simulation failed. (my_acos1 is added core generator file in my project).
I'm using windows 7 , ISE 14.7 and MATLAB 2014a.

could someone please help resolve this issue.

Thank you.
 
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It looks like the fundamental problem is that it can't find the mif file. Have you tried synthesizing the design? Does it synthesize ok? What are you using for a simulator?
 

It looks like the fundamental problem is that it can't find the mif file. Have you tried synthesizing the design? Does it synthesize ok? What are you using for a simulator?

yes synthesis is succesfull. Im using ISE 14.7 simulator

The .mif file might be in the wrong folder.

actually the a core generator my_acos1.xco is added as source file to top module. Now when simulated ... there is an error showing : cannot open my_acos1.mif
 
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yes synthesis is succesfull. Im using ISE 14.7 simulator



actually the a core generator my_acos1.xco is added as source file to top module. Now when simulated ... there is an error showing : cannot open my_acos1.mif
As FvM pointed out, your .mif file is probably in the wrong location. There's some file that is referencing the .mif file and is probably the culprit. Search for a file that references your .mif file, and check that the path is correct.
 

The simulink model is added as .ngc file to topmodule.vhd
I have configured system generator and simulated top module it is showing these errors-
warning: HDL compiler :89 - filename.ngc remains a black-box since it has no binding entity
error : HDL compiler :1030- N:/P.20131013/rtf/hvdl/src/xilinxCoreLib/BLB_MEM_GEN_V7_3.vhd
error: Line 2797: cannot open file.my_acos1.mif (.... my code has only 600 lines)
error:simulator:777 - static elaboration of top level VHDL design unit module_name in library work failed
 

As FvM pointed out, your .mif file is probably in the wrong location. There's some file that is referencing the .mif file and is probably the culprit. Search for a file that references your .mif file, and check that the path is correct.
okay.
when core generator files (.coe)are created automatically .mif file is created along with it when synthesized. The synthesis was successful but while simulating as this .mif file is first in the order of simulation and so the entire simulation failed.
And I have checked the location of .coe file it was in the same directory of the project.
 

If you can't or won't look for the file that calls out the .mif file to see if it is looking for the file in a specific directory....

Try copying the .mif file (from wherever core generator created it and the .coe file) to the where ever the simulation is being run. I've seen more than one time that such files are expected to be in the same directory where the simulation is running and not buired in some hierarchical directory path.
 

The simulink model is added as .ngc file to topmodule.vhd
I have configured system generator and simulated top module it is showing these errors-
warning: HDL compiler :89 - filename.ngc remains a black-box since it has no binding entity
error : HDL compiler :1030- N:/P.20131013/rtf/hvdl/src/xilinxCoreLib/BLB_MEM_GEN_V7_3.vhd
error: Line 2797: cannot open file.my_acos1.mif (.... my code has only 600 lines)
error:simulator:777 - static elaboration of top level VHDL design unit module_name in library work failed
YOUR code may only have 600 lines, but the file referenced in the error message obviously has at least 2797 lines. As I said, LOOK FOR THE FILE REFERENCING THE .MIF FILE. If you look at line 2797, you should see the path there.

I'm not suggesting you change that file, but maybe put a copy of the .mif file where it can be found.
 

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