Xilinx settings for place and route or synthesis

[master.ro]

Hello!
I have minimal experience with Xilinx and now I have to do a project with itXilinx.
For this I use Xilinx 8.1i.
Which are the settings for best result in synthezis, place and route?

 

[bansalr]

Re: Xilinx Settings

For synthesis define clocks frequency, retiming option.
optimization for speed.

2. For place and route define clock frequency. give map and par effort level high.
provide a constarint file with pin locking, clock frequency, false path.

 

[master.ro]

Re: Xilinx Settings

Thank you!
I'm waiting more tips & tricks in Xilinx utilization and configuration!

 

[super luan]

Xilinx Settings

For synthesis,you can do as what bansalr said.
But for p&r, you should set high level restrainedly.
Because high leve will cost long time.
You can find " Design Performance and Runtime Strategies For FPGAs" in ISE HELP. This will be helpful for you.
Thanks!
super luan

 

[s3034585]

Re: Xilinx Settings

Hi
You can also set the nelist option dependaning on your design in synthesis. I agree with super luan for setting the effort level to high for P&R. It also depands on how big is ur design. If your design is almost using approx 95% plus slices in the fpga then in this case you might set the effort level to high. It take a very long time to complete. you can also generate post place and route models for post P&R functional verification.

tama

 

[master.ro]

Re: Xilinx Settings

Thank you!