XILINX - Problems with sys_clk in UCF file for DDR2

[erikwikt]

XILINX - FPGA clocking problem

Hello. I just want to start with that I'm very new to FPGA design so my knowledge at the time very limited. I'm using the Virtex®-5 XC5VLX110T that is mounted on the XILINX™XUPV5-LX110T development board.

I'm trying to make a "hardware test-bench" for a DDR2 memory controller that I have generated from XILINX MIG 3.61 core generator. Its just a simple state machine that write to some locations in the memory and then reads from them.

The problem that I have now is that I can't really clock the design. When I was generating the memory controller I choose a differential clock design and PLL as clock source which gave me four clock inputs. One 200Mhz and one "user clock" that sets the operating frequency for the memory controller. I have been able to find a clock source for the 200Mhz clock and specified that in my UCF file but I cant find a clock source for the "user clock" that is differential.

I know there is a clock-source on the board that is identified as "USERCLK" that runs in 100Mhz. The two problems with this one is that its single-ended and it only runs in 100Mhz which is to slow for the memory controller since the manual for the controller says that the "user clock" has to be between 125Mhz and 266Mhz.

My first try was then to just route the incoming 200Mhz differential clock signal to both the differential clock pairs on the design, this gave me this following error messages:

Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible.
Further explanation:
The component already has an input slave buffer.
Symbols involved:
PAD symbol "clk200_n" (Pad Signal = clk200_n)
SlaveBuffer symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/SLAVEBUF.DIFFIN" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/SLAVEBUF.DIFFIN)
SlaveBuffer symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/SLAVEBUF.DIFFIN" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/SLAVEBUF.DIFFIN)


Pack:1107 - Pack was unable to combine the symbols listed below into a single IOB component because the site type selected is not compatible.
Further explanation:
The I/O component already owns an input buffer.
Symbols involved:
PAD symbol "clk200_p" (Pad Signal = clk200_p)
DIFFAMP symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.IDLY_CLK_INST/IBUFDS" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/clk200_ibufg)
DIFFAMP symbol "MEM_CTRL/u_ddr2_infrastructure/DIFF_ENDED_CLKS_INST.SYS_CLK_INST/IBUFDS" (Output Signal = MEM_CTRL/u_ddr2_infrastructure/sys_clk_ibufg)

If someone could please explain what this messages means that would really be helpful.

Thank you in advance.

-Erik

 

[erikwikt]

Re: XILINX - FPGA clocking problem

Hello again, been trying to fix the problem.

I decided to use the on-board 100Mhz clock and use a DCM to generate the 200Mhz clock that I need for the "user clock". For this I again used the ip core generator that comes with XILINX and it worked good during simulation.

I then tried to implement it in my design but when I try to synthesize it I get the following error messages:

NgdBuild:455 - logical net 'INTERNAL_sys_clk_n' has multiple driver(s):
pin O on block INTERNAL_sys_clk_nLogicTrst1 with type LUT2,
pin PAD on block INTERNAL_sys_clk_n with type PAD

NgdBuild:924 - input pad net 'INTERNAL_sys_clk_n' is driving non-buffer primitives:
pin O on block INTERNAL_sys_clk_nLogicTrst1 with type LUT2

NgdBuild:455 - logical net 'INTERNAL_sys_clk_p' has multiple driver(s):
pin O on block INTERNAL_sys_clk_pLogicTrst1 with type LUT2,
pin PAD on block INTERNAL_sys_clk_p with type PAD

NgdBuild:924 - input pad net 'INTERNAL_sys_clk_p' is driving non-buffer primitives:
pin O on block INTERNAL_sys_clk_pLogicTrst1 with type LUT2

My interpretation of the error massages is that the signals sys_clk_n and sys_clk_p has more drives connected to them what could lead to unknown values if more then one driver tries to write at the same time (right?). Don't really know that NgdBuild:924 means though.

Here is a small part of my code if it helps to see my mistake:

library ieee;
use ieee.std_logic_1164.all;

entity Top_Memory_Test is
  
  port (
    sys_clk               : in    std_logic;
    ....
    clk200_p              : in    std_logic;
    clk200_n              : in    std_logic;
    ....
    );
  
end Top_Memory_Test;

architecture behavior of Top_Memory_Test is

	COMPONENT Top_DCM
	PORT(
		CLK_IN : IN  std_logic;
		....
		CLK_OUT_P : OUT  std_logic;
		CLK_OUT_N : OUT  std_logic
	  );
	END COMPONENT;

  component Memory_SM
    .....  
  end component;
  
  component DDR2_MEM
    .....
  end component;
  
  signal INTERNAL_sys_clk	        :    std_logic;
  signal INTERNAL_sys_clk_p             :    std_logic;
  signal INTERNAL_sys_clk_n             :    std_logic;

  
begin  -- behavior
  
  INTERNAL_sys_rst_n    <= sys_rst_n;
  INTERNAL_sys_clk	<= sys_clk;
  
	uut: Top_DCM PORT MAP (
		 CLK_IN => INTERNAL_sys_clk,
		 RST_IN => INTERNAL_sys_rst_n,
		 CLK_OUT_P => INTERNAL_sys_clk_p,
		 CLK_OUT_N => INTERNAL_sys_clk_n
	  );
  
  MEM_SM : Memory_SM generic map (....) port map (....);
  
  MEM_CTRL : DDR2_MEM generic map (....) port map (
                          sys_clk_p => INTERNAL_sys_clk_p,
                          sys_clk_n => INTERNAL_sys_clk_n,
			);
end behavior;

 

[samuraign]

I think you should consider inserting BUFG & IBUFG's.

If it is Virtex-5 Development board then your vendor might be providing you a reference DDR2 controller.
Please consider to check it.

 

[erikwikt]

I have changed it now samuraign. The biggest problem that I had was that I was trying to generate a 200Mhz from 100Mhz source, make it differential, duffer it with a IBUFGDS_LVPECL_25 and feed the PLL to generate the clocks for the memory controller.
Which of course doesn't make any sense.

So I made a new PLL that was designed to take in a 100Mhz clock and output a 200Mhz to the design and I connected the external 100Mhz on-board clock to the design and buffered it with a IBUFG. Thank *** for XILINX manual about the Virtex 5 (UG190 [v5.4]).

Now can I compile the design without any errors! Just have to make the state machine to work now.....