Chops211
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Quick question:
When implementing logic in a PLD using VHDL, the following code will synthesize into comparators and adders:
output <= '0' & input when input < X"28" else
'0' & input + X"18" when input < X"50" else
'0' & input + X"74" when input < X"74" else
'1' & input + X"50" when input < X"99" else
'1' & X"E8";
If i was to make a large LUT using the presolved values of this equation, how will the ISE software synthesize the design? As a one clock cycle LUT or condense it into the previous design using comparators and adders? It is basically a time difference, is it worth while to code the entire truth table? Speed is not a concern, power usage is more important.
Thanks
When implementing logic in a PLD using VHDL, the following code will synthesize into comparators and adders:
output <= '0' & input when input < X"28" else
'0' & input + X"18" when input < X"50" else
'0' & input + X"74" when input < X"74" else
'1' & input + X"50" when input < X"99" else
'1' & X"E8";
If i was to make a large LUT using the presolved values of this equation, how will the ISE software synthesize the design? As a one clock cycle LUT or condense it into the previous design using comparators and adders? It is basically a time difference, is it worth while to code the entire truth table? Speed is not a concern, power usage is more important.
Thanks