Titormos
Newbie level 2
Hello,
I've been struggling with the pci-e interrupts, and the pci itself, for quite some time. Unfortunately there are a few well-written guides as far as I'm concerned.
I would like to ask the following:
0) which one is simpler to implement, msi or msix , taking into account that we need more than 1?
1) How do you actually send data? Do you need axi, axi4, or there is a simpler way like a PIO to do it simply.
1.1) how do you generate an msi? Do you need to send data along with it?
2) What happens when msi or msix gets generated? I believe they are integrated into the packet, e.g. a specific value is assigned in the header.
2) How does your code(fpga side) interface with each BAR.
and last but not least :
3) [briefly]What are the steps to generate a packet and an interrupt in the PCIe?
I know that it is a little bit confusing how I wrote the questions, but the user guides do not help me the way I want. Any feedback is welcome and also any pointer for a simple guide to those things.
Thanks in advance.
I've been struggling with the pci-e interrupts, and the pci itself, for quite some time. Unfortunately there are a few well-written guides as far as I'm concerned.
I would like to ask the following:
0) which one is simpler to implement, msi or msix , taking into account that we need more than 1?
1) How do you actually send data? Do you need axi, axi4, or there is a simpler way like a PIO to do it simply.
1.1) how do you generate an msi? Do you need to send data along with it?
2) What happens when msi or msix gets generated? I believe they are integrated into the packet, e.g. a specific value is assigned in the header.
2) How does your code(fpga side) interface with each BAR.
and last but not least :
3) [briefly]What are the steps to generate a packet and an interrupt in the PCIe?
I know that it is a little bit confusing how I wrote the questions, but the user guides do not help me the way I want. Any feedback is welcome and also any pointer for a simple guide to those things.
Thanks in advance.
Last edited: