I just looked at your simulation output.
You are manually generating the clock, therefore you've only generated four rising clock edges. The .xco file has a latency setting of 16, which means you need 16 clocks from the time the input data is applied to the dividend and divisor inputs until the quotient and fractional outputs are available.
Try using something like this inside your testbench instead of the brute force assignments...
Code Verilog - [expand] |
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| initial begin
clk = 0;
forever #10 clk = clk;
end
initial begin
// apply a reset for 100 ns
rst = 1;
# 100;
rst = 0;
end
always @(posedge clk) begin
if (rst) begin
dividend = 0;
divisor = 0;
end else begin
dividend = $random;
divisor = $random;
end
end |
Note: code is untested.