Xilinx LogiCore Block Problem

[koshmar29]

Hello,

I want to use the Divider Generator v3.0 in Xilinx Webpack v14.7 to perform division on my Spartan 3E. I generated a block using the following settings :
Algorithm type: radix2
Dividend and Quotient Width: 12 bit
Divisor Width: 12 bit
Remainder Type: Remainder
Fractional Width: 12
Operand Sign: Signed
Latency Configuration: AUtomatic
Latency: 16
Clocks per Division: 1

I wrote a simple testbench simulating various dividends and divisors, but no matter what I do the quotient is always 0. I'm not using any external signals to control the divider, so I'm confused as to why it's not working. I have limited experience working with the LogiCore Blocks, so if anybody can help me set it up properly, I'd greatly appreciate it.

 

[ads-ee]

Can you post your testbench and perhaps the ISIM or Modelsim waveforms of the ports of the Divider core?

 

[mrflibble]

In addition to ads-ee's request, best also to post the .xco file for the divider core. That way others can reproduce your testbench should that be required.

 

[koshmar29]

I uploaded the .xco file along with my testbench and its waveform.
Thank you for your assistance~

 

[ads-ee]

I just looked at your simulation output.

You are manually generating the clock, therefore you've only generated four rising clock edges. The .xco file has a latency setting of 16, which means you need 16 clocks from the time the input data is applied to the dividend and divisor inputs until the quotient and fractional outputs are available.

Try using something like this inside your testbench instead of the brute force assignments...

---

Code Verilog - [expand]
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initial begin
    clk = 0;
    forever #10 clk = clk;
  end
 
  initial begin
    // apply a reset for 100 ns
    rst = 1;
    # 100;
    rst = 0;
  end
 
  always @(posedge clk) begin
    if (rst) begin
      dividend = 0;
      divisor = 0;
    end else begin
      dividend = $random;
      divisor = $random;
    end
  end

---

Note: code is untested.

 

[koshmar29]

I just looked at your simulation output.

You are manually generating the clock, therefore you've only generated four rising clock edges. The .xco file has a latency setting of 16, which means you need 16 clocks from the time the input data is applied to the dividend and divisor inputs until the quotient and fractional outputs are available.

Try using something like this inside your testbench instead of the brute force assignments...

---

Code Verilog - [expand]
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initial begin
    clk = 0;
    forever #10 clk = clk;
  end
 
  initial begin
    // apply a reset for 100 ns
    rst = 1;
    # 100;
    rst = 0;
  end
 
  always @(posedge clk) begin
    if (rst) begin
      dividend = 0;
      divisor = 0;
    end else begin
      dividend = $random;
      divisor = $random;
    end
  end

---

Note: code is untested.

Thanks for your suggestion. I tried running your testbench and the output is coming out all wrong (see waveform).

 

[dipin]

hi

Thanks for your suggestion. I tried running your testbench and the output is coming out all wrong (see waveform).

nothing is wrong in those outputs. check every input after 16 clockcycle .your latency will be 16 clock cycle for a 12 bit input. so output will come after 16 clockcycle.

regards

 

[koshmar29]

Ah, thank you for pointing it out.