I'm with TrickyDicky on this...So you would suggest using ModelSim for the static timing simulation?
Also, are you aware of any fast tutorial on how to do that?
Just to add - that in my only brush with an ASIC, I dont think there was even a plan to do a timing simulation - just Lots and lots of RTL verification (both UVM and formal) followed by FPGA emulation (though it all got cancelled before we even got to proper verification).
Basically tools are good enough now that as long as you have good code practice, the synthesised design will match the RTL.
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Plus Ive only ever seen 1 proper synth bug where RTL didnt match the synthesised design, and that was in a Xilinx IP block in ISE 14.7!!
Thank you both for your replies, i guess will simulate only post-synthesis model then!
Why? Thats what we've been telling you not to bother with. Just do an RTL simulation.
Ok that clears it up. But is behavioral simulation enough for that?
By the way, I somehow managed to run a post-route simulation and generated totally different ( wrong )results in comparison with the behavioral simulation.
Ok that clears it up. But is behavioral simulation enough for that?
By the way, I somehow managed to run a post-route simulation and generated totally different ( wrong )results in comparison with the behavioral simulation.
This can also occur when doing timing simulation as the netlist will have delays on the IO that don't exist in the behavioral code, which means your testbench can cause problems. The other issue is if you don't correctly use the GLBL reset net in Xilinx to reset the entire designs FFs to their reset state, emulates the after configuration state of a Xilinx FPGA. If you don't use it all FFs that are not explicitly reset will end up being X until updated with a valid input.If this happens, it will usually be because of poor coding style, with signals missing from sensitivity lists, latches etc.
Why not post some code so we can have a look?
We did it to verify that the layout was done correctly and the back annotated SDF with all the included parasitics still resulted in the design functioning as intended. We also ran the test vector suite generated by the DFT tool to sign off on the test vectors before tape out. Not sure how much of these are done for todays ASIC designs, our largest was only 2-3 million gates.ThisIsNotSam said:ASIC people still do gate level simulation. It still is very useful for finding top-level connectivity issues. But in general you do trust that the synthesis output matches the RTL just fine.
I will check the reset of the FFs , as i have FFs that get reset not by the "global" reset signal but by changing of an inner state ( from an FSM ) ( i guess that's what is Tricky talking about when saying poor coding style ).
The design consists of about 14 modules, so in order to make sense, i have to upload all modules and i doubt someone will go over so many lines.
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