Ok I know this should just be a "go read the manual" thing, but I have and it still doesn't work with even the simplest modules. Can someone explain what I'm doing wrong.
My Procedure:
1) new project
2) new module: test.v
Code:
module test(input clk, output div);
reg out;
assign div = out;
always @(posedge clk)
out = !out;
endmodule
3) new Verilog Test Fixture: tb.v
Code:
module tb;
// Inputs
reg clk;
// Outputs
wire div;
// Instantiate the Unit Under Test (UUT)
test uut (
.clk(clk),
.div(div)
);
initial begin
// Initialize Inputs
clk = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #5 clk=!clk;
endmodule
4) Switch to behavioral simulation
5) Select tb.v
6) double clicked Simulate Behavioral Model
7) Results:
Console Output:
Code:
INFO: There is another simulation running in the same directory. Using database file name isim1.wdb.
ISim O.61xd (signature 0x1cce1bb2)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Time resolution is 1 ps
Simulator is doing circuit initialization process.
Finished circuit initialization process.
As you can see, this should be a simple clock divider, but nothing happens. Does it have something to do with the first line on the console: "INFO: There is another simulation running in the same directory. Using database file name isim1.wdb." ?
You are not resetting out register. Registers that are not initialized are x. Thats why this x value gets assigned to div.
Please reset the signal out like
always @(posedge clk or posedge rst)
if(rst)
out <= 1'b0
else
out <= ! out;
Then make reset another input to test and also put reset in test bench.