cyboman
Member level 4
i'm new to digital design and fpgas. i have started using Xilinx ISE WebPack 11.1 (instead of Aldec Active HDL 7.1 SE) for synthesis and implementation on Nexys2 board. i'm trying to figure out what startup clock option is and what it is used for. the tutorial i went through simply told me to use JTAG as a startup clock but it was not explained why. the options that i have available for startup are: JTAG, CCLK and User clock. i'd would really appreciate an explanation about the difference between these clocks, how i can supply these clocks to my design and why i need to use JTAG?
thanks in advance.
thanks in advance.