Hello everyone,
Im implementing a LDPC ( low density parity check ) decoder on ML605 evaluation platform ( the device is a large Virtex6 ).
After synthesis step, the resources used according to the report is 29% Registers and 61% LUTs with an actual ratio of 83.
After the map process, these resources decrease even further, leading the LUTs needed to only 50-52%.
The problem is that , at the PAR step, the router detects "a dense , congested design" and therefore stops leaving around 90k nets unrouted.
Any suggestions on how i can overcome that? The resources needed are not so extreme i think.
Note that i havent used any constraints on the clock frequency, neither have i done any floorplanning.
Thank you in advance,
Nikos