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Xilinx ISE implementation stage issues

promach

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Could anyone help with the series buffer and multiple drivers issues ?

1624116267772.png
 

barry

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You have many, many, many errors here. The messages tell you where to look.

the first one looks like you’ve got two IBUFDS in series.

the third one says you’ve got two signals driving net “data-to-ram<105>”.

and so on.

you need to go back and look at your code.
 

promach

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"user_desired_extra_read_or_write_cycles" is not differential signal, so I do not understand why the tool complains about IBUFDS stuff
 

barry

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I don’t really know System Verilog, but it looks to me like you’ve got an IF statement embedded in an assignment statement (line 1135); maybe that works in SV, but it looks like a mess to me. Maybe that’s causing an error? I’m just having a hard time following your code.
 

promach

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Code:
wire extra_read_or_write_cycles_had_passed  // to allow burst read or write operations to proceed first
        = (postponed_refresh_timing_count ==
`ifndef XILINX
                user_desired_extra_read_or_write_cycles*TIME_TREFI[0 +: $clog2(TIME_TREFI)]);  // for verilator warning
`else
                user_desired_extra_read_or_write_cycles*TIME_TREFI[0 +: 9]);
`endif

You mean this code snippet ? Are you familiar with the use of ifdef as well as endif ?
 

barry

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Code:
wire extra_read_or_write_cycles_had_passed  // to allow burst read or write operations to proceed first
        = (postponed_refresh_timing_count ==
`ifndef XILINX
                user_desired_extra_read_or_write_cycles*TIME_TREFI[0 +: $clog2(TIME_TREFI)]);  // for verilator warning
`else
                user_desired_extra_read_or_write_cycles*TIME_TREFI[0 +: 9]);
`endif

You mean this code snippet ? Are you familiar with the use of ifdef as well as endif ?
Yeah, that. As I said, I don't really know SV, but that just looks little unwieldy to my untrained eye.
 

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