[SOLVED] Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

[Alper özel]

I am trying to see the schematic output of my verilog module in Xilinx ISE. However, I am getting this silly error:

ERROR:Xst:2369 - Empty project file "C:\Users\aozel\Desktop\Verilog Projects\trial_one\trial_one\receive_byte.prj"

I ve already tried restarting both ISE and computer but they did not help. So I am asking for help from experienced FPGAdevelopers. Here the top module I want to sythesize:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:19:35 01/05/2016 
// Design Name: 
// Module Name:    receive_byte 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
`include "counter_4.v"
module receive_byte(
	input [0:0] clk,
	input [0:0] enable_to_rx_byte,
	output reg [7:0] rx_byte,
	output reg [0:0] rx_done,
	input [0:0] sda_to_rx_byte,
	output reg [0:0] scl_flag_from_rx_byte,
	input [3:0] flags_from_ctr_4,
	output reg [0:0] en_to_ctr_4,
	output reg [0:0] rst_to_ctr_4,
	output reg [0:0] rst_to_ctr_4_done,
	output reg [2:0] rx_ctr,
	output reg [0:0] mode_to_ctr_4,
	input [15:0] ctr_4
);

parameter data_rate_khz = 0;
integer N_to_scl_div = 500000 / data_rate_khz; 

always @(posedge clk) begin
	if (enable_to_rx_byte !== 1'b1) begin
		rx_done <= 1'b0;
		en_to_ctr_4 <= 1'b0;
		rst_to_ctr_4 <= 1'b0;
		rx_ctr <= 3'b111;
	end
	else if (enable_to_rx_byte === 1'b1) begin
		en_to_ctr_4 <= 1'b1;
		mode_to_ctr_4 <= 1'b1;
		if (rx_done !== 1'b1) begin
			if (flags_from_ctr_4[0] == 1'b1 && flags_from_ctr_4[3] === 1'b0) begin
				scl_flag_from_rx_byte <= 1'b0;
				if (ctr_4 == N_to_scl_div * 3 / 4) begin
					rx_byte[rx_ctr] <= sda_to_rx_byte;
					if (rx_ctr == 3'b0) begin
						rx_done <= 1'b1;
					end
					else if (rx_ctr != 3'b0) begin
						rx_ctr <= rx_ctr - 1;
					end
				end
			end 
			else if (flags_from_ctr_4 == 4'b0000) begin
				scl_flag_from_rx_byte <= 1'b1;
			end
			else if (flags_from_ctr_4 === 4'b1000) begin
				scl_flag_from_rx_byte <= 1'b1;
			end
		end
	end
end

always @(negedge clk) 
begin: RESETTER_TO_CTR_4
	if (en_to_ctr_4 !== 1'b1) begin
		rst_to_ctr_4 = 1'b0;
		rst_to_ctr_4_done = 1'b0;
	end
	else if (en_to_ctr_4 === 1'b1) begin
		if (!rst_to_ctr_4_done) begin
			rst_to_ctr_4 <= 1'b1;
			rst_to_ctr_4_done <= 1'b1;
		end
		else if (rst_to_ctr_4_done) begin
			rst_to_ctr_4 = 1'b0;
		end
	end
end

counter_4 u1(
	.rst       (rst_to_ctr_4),
	.en        (en_to_ctr_4),
	.mode      (mode_to_ctr_4),
	.clk       (clk),
	.flags     (flags_from_ctr_4),
	.comp_A    (N_to_scl_div / 2),
	.comp_B    (0),
	.comp_C    (0),
	.comp_D    (N_to_scl_div),
	.ctr       (ctr_4)
);

endmodule

Here is the counter_4 module:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:36:48 01/05/2016 
// Design Name: 
// Module Name:    counter_4 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter_4(
	input [0:0] rst,
	input [0:0] en,
	input [0:0] mode,
	input [0:0] clk,
	output reg [3:0] flags,
	input [15:0] comp_A,
	input [15:0] comp_B,
	input [15:0] comp_C,
	input [15:0] comp_D,
	output reg [15:0] ctr
);

//reg [15:0] ctr;

always @(posedge clk) begin
	if (rst) begin
		ctr = 16'b0;
		flags = 4'b1000;
	end
	else if (!rst) begin
		if (en) begin
			ctr = ctr + 1;
			if (mode) begin
				if (ctr != comp_D) begin
					if (ctr == comp_A && comp_A != 16'b0) begin
						flags[0] = 1'b1;
					end
					else if (ctr == comp_B && comp_B != 16'b0) begin
						flags[1] = 1'b1;
					end
					else if (ctr == comp_C && comp_C != 16'b0) begin
						flags[2] = 1'b1;
					end
				end
				else if (ctr == comp_D && comp_D != 16'b0) begin
					flags = 4'b0;
					ctr = 16'b0;
				end
			end
			else if (!mode) begin
				if (ctr == comp_A && comp_A != 16'b0) begin
					flags[0] = 1'b1;
					ctr = 16'b0;
				end
			end
		end
		else if (!en) begin
			flags = 4'b1000;
		end	
	end
end

endmodule

 

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Re: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

You obviously didn't even try a quick google search for the xst:2369 error message, otherwise you would have found this.

It suggests that you close ISE and reopen it to work around the problem. I think ISE has problems with loading the project file sometimes. I recall having similar issues, when I would use the GUI (I usually script the build flow in ISE).

 

[Alper özel]

Re: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

I ve already tried restarting both ISE and computer but they did not help.

But I already said that did not work. Something else is gong on. I ve seen it.

 

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Re: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

But you didn't recreate a NEW project file, which was also mentioned as a having worked for someone else.

Open the .prj file in a text editor and see if there is anything in it. The problem is not likely to be your code, glancing over it there's nothing in it that looks obviously wrong. Though there are things I think are done that are not the best way to write code.

 

[Alper özel]

Re: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

I created new project and it worked, I must have missed that part. Thanks a lot!

But can you please tell me what part of the code would be better? I can use good critisism. Thanks.

 

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Re: Xilinx ISE ERROR:Xst:2369 - Empty project file "C:\xxxx" what is it about?

But can you please tell me what part of the code would be better? I can use good critisism. Thanks.

e.g.

	input [0:0] clk,
	input [0:0] enable_to_rx_byte,

The extra 0:0 is making this a bus of 1 bit, this is not necessary and usually is only seen when you have code that is auto generated by some tool.

Tabs, don't use tabs, inevitably spaces and tabs will get mixed in a file and then you have a very ugly file unless the next person has their tab setting set exactly the same. Only use spaces so the formatting never changes no matter what the tab setting is. A decent text editor will have the ability to insert spaces when the tab key is pressed.

if (!enable) begin
if (enable = 1'b0) begin

Pick one or the other and stick with it. Don't mix between the two. Personally I prefer the first as it requires less typing ;-).

always @(posedge clk) begin
	if (rst) begin
		ctr = 16'b0;
		flags = 4'b1000;

Using blocking assignments (=) in a edge sensitive always block.
You should stick with using blocking (=) with combinational always blocks (i.e. always @*) and use non-block (<=) with edge sensitive always blocks. And never mix the two. If you stick with those rules you'll never run into the ugly simulation/synthesis mismatch problems you can get when not following them.

integer N_to_scl_div = 500000 / data_rate_khz;

N_to_scl_div is 32-bits wide and may not be optimized to the 19-bit wide maximum. This is not an error, but I've seen it happen before when using XST.