Xilinx IP generated core does not meet timing constraints

[mbenton]

Hello,
I generated a fir filter using IP coregen, but when trying to build the bitstream I get timing constraints errors and a lot of wires are left unconnected.
This happens if if set the filter's clock frequency at 200Mhz(250Mhz is max in the coregen window) and use a DCM to double my board frequency(from 100 to 200MHz).
If I set the filter's clock frequency at 100Mhz it works without any problems,but the number of resources occupied doubles and I cant really afoard that on the long run because I will be using a lot of filters.
I also mention that the core generator's settings are set to match my fpga board. I can't understand why this happens since core gen tells me that the maximum frequency allowed is 250 MHz, and since I can create a bitstream which contains 5 filters running at 100Mhz(each occupying almost double the resources of a filter running at 200MHz ).
I find it odd, given the things mentioned above, that I cant implement a DCM and a filter running at 200MHz.

Thank you,
Benton

 

[farhada]

This depends on the FPGA you are using, the speed grade of your FPGA and many other issues.

You can't just create an IP and since it says it supports 250MHz, assume that it works with the slowest device in the family.

 

[mbenton]

Re: Xilinx IP generated core does not meet timing constraint

farhada thank you for your fast answer.
Please correct me if I'm wrong, but I thought the maximum clock frequency allowed in the core generator window depends on the board, package and speed grade. For example if I choose a Virtex5 the maximum allowed frequency is 500Mhz. For my board it tells me that it is 250MHz.

 

[farhada]

Re: Xilinx IP generated core does not meet timing constraint

You are right, my mistake, when you chose your board, you get the right delays for your device.

But having said that, most of the cores generated by Xilinx depend highly on what else you have in your design. One simple addition that will give you a better timing is to add output buffer on all the signals out of the IP and make sure that the signals going into your IP are all buffered properly. It can be useful to add an extra buffer to the output signals if you have wide busses to make it easier for P&R to calculate the delay.

But again, it depends highly on the implementation of the IP into your design and not the IP itself. You can test this simply by implementing the IP into a simple design and then compare it with the result from your actual design.

It is also important to find where in your data path you have a problem and try to figure out what you can do to fix that.

 

[shitansh]

Re: Xilinx IP generated core does not meet timing constraint

one more important thing is to give proper timing constraint while compiling design.

For example IP generated has multiple clocks and depending on nature of other clock domain you need to spacify constraint correctly. say generated clock constraint, derived clock constraint,
multicycle paths , false pats...etc If you have not specify constraint for other clock domain then timing analysis tool will perform timing check with respect to your main clock and you will get failing paths.

this is one case, so for timing related failing path, apart from other causes it is necessary to give proper timing constraint too.

HTH
Shitansh Vaghela