xilinx ibis modeling on the cheap

[eda_ia]

I'm trying to do a project that involves taking in data at a decent rate(50-100MHz), but I'm a poor college student who can't afford software packages worth thousands of dollars to do signal integrity analysis. The ibis data seems straight forward enough, but I was wondering if anyone knows how the constraints, and or static timing information relates to these ibis data points. For example:

-does the Xilinx static timing information tell how long the signal on an input has to remain stable in order to be sampled correctly.

-When data is being send out on a pin do I assume that the output starts to transition after the pad delay, or does the clock to pad delay give you when the ibis VT curve reaches some threshold like 50% or 90% VCC.

Pointing me in the right direction on these issues would really help me out.

 

[b00merang]

Hello,

If you have the IBIS model available, then you're about half-way there. Most CAD tool (i.e. even the cheap ones) can read Ibis files. I would suggest setting it in in a testbench using a randon bit stream of data. This will allow you to look at the eye-diagram of the model (for the various speed rate of your input clk). From the eye-opening, you can extract most of the information you need.

Regards,