Xilinx FPGA timing Constraint

[amin_8460]

Hi there

I am using a SPARTAN6 speed grade 3 and there is a high speed SDR SRAM In my board. I've used PLL to generate clock and out to SRAM.
I set timing constraint but the max frequency I achieved is 125 MHz. If I increase the output clock of PLL to 150 MHz I have timing constraint error: "Slack in some nets is -3.447ns."
How can I increase the max frequency? what should I do in timing constraint?

Thanks
Amin

 

[TrickyDicky]

to increase the fmax, you need to improve the pipelining in the design - ie. shorten the logic gap between registers. The timing report should show you where the failures are, so you can fix the logic (ie add more registers) to this path (obviously, going back to simulation to ensure you didnt break something else doing this).

 

[amin_8460]

The delay error is between two Flip Flop and so the pipeline method could not use in this situation.
My problem is routing not synthesize.

 

[barry]

Do you have a lot of combinatorial logic between the two flip flops? That could cause excessive delay, and that's where you'd need to add pipeline stages.

 

[mrflibble]

The delay error is between two Flip Flop and so the pipeline method could not use in this situation.
My problem is routing not synthesize.

Sure you can. The problem quite often is "between 2 FFs". And such problems can be solved by fixing the design and re-synthesizing. As the others have said, you have to go through the timing report and investigate the offending paths. Chances are good you have too many logic levels. It'll report the total delay, and how much of that is due to logic, and how much of that is due to routing. If it's logic ... pipeline it. If it's routing ... other things. But it'll probably be logic.

In any event, before you say I CANNOT PIPELINE IT ... tell us what the # of logic levels, logic delay , routing delay , etc is for say the 3 slowest paths.