Xilinx Floorplaner and FPGA Editor

[osbourne]

fpga editor

Hi,

I'm a beginner in FPGA design. I'm currently asking myself, if Floorplaner and FPGA Editor are really needed to make an FPGA design. Are these tools rarely used or is there somebody who extensively uses them?

In which situations shall I use them ?
If I have a very large design, does it make sense to manually place and route (there are hundreds of lines and compnents in the FPGA Editor) ?

Regards,
Osbourne

 

[gliss]

view/edit routed design (fpga editor)

Most people I know don't use those tools very much. But, as FPGA's get more compolex maybe back end stuff like floorplanning will be become more common.
If the automatic P&R tools realize your design such that the constraints are met, then I see no reason to do manual P&R.

 

[osbourne]

fpga editor tutorial

Hi,

even if it is not much used, I'd like to learn how it could be used.
How can I learn it ? My design is very large and there are hundreds of lines and hundreds of placed components. I cannot imagine what could be done using FPGA Editor because I don't know the meaning of every single line and placed component.

Is there a comprehensive tutorial available with examples ?

regards,
Osbourne

 

[echo47]

xilinx floorplanner tutorial

I've crammed a lot of fast stuff into big Virtex-II chips, and I've never used floorplanner. Instead, I specify location constraints on my critical modules to prevent the place/route tools from creating a large bowl of spaghetti. With those constraints, the place/route finishes quicker, and the chip runs at higher MHz.

I use FPGA Editor frequently to inspect my layouts. I want to make sure place/route did approximately what I expected it to do. I also use it to examine the slowest routes, so that I can try to think of ways to speed them up. I almost never use FPGA Editor to edit anything.

 

[samcheetah]

launch fpga editor

i heard that these are used when you need to eliminate the critical paths. now, i havent made such a big design that has critical paths so i havent seen them.

and thanx echo47 for the nice tip

 

[echo47]

view/edit placed design (fpga editor)

Here's a quickie FPGA Editor tutorial for checking timing:
1. Launch FPGA Editor and open your NCD file.
2. In your List1 window, select "All Nets".
3. In your List1 window, select all the nets (use click and shift-click).
4. In your menu, click Tools -> Delay.
5. In your List1 window, click "Max Pin Delay" to sort that column.
6. Scroll down to find the slowest net. Click it to highlight the trace in your big window. Then zoom in to see why it's so slow (probably because it's long or high-fanout).