XILINX dual-port ram / VIRTEX4 / CORE Generator

[keano]

xilinx dual port memory

Hi,

Is there a way to visualize the contents of a dual-port ram on MODELSIM Simulator?

thanks

 

[echo47]

xilinx dual port ram

You can open a "memory pane". On the Main window, click the Memories tab, and then the name of your RAM variable. It shows the memory contents in binary, hex, decimal, whatever. You can also edit individual values.

I'm not sure why you mentioned Virtex 4 and core generator in your message subject. Those topics seem unrelated to viewing HDL memory arrays.

 

[keano]

xilinx core generator + dpram

Well I'm working on Virtex4 FPGA and I generated a dual port block ram using CORE Generator. The problem is that I can't find a signal that represents the memory contents. Any idea?

Thanks

 

[echo47]

xilinx virtex 4 memory infer

Oh. Another good reason to avoid using Xilinx cores.
I suggest writing ordinary HDL to describe your memory, and let the synthesizer infer the Block RAM.

 

[keano]

xilinx core generator memory

what are the other reasons to avoid using xilinx coregen?

 

[echo47]

dual port block ram

So far, I have been disappointed with every Xilinx core I've tried. They are either too bulky, or too slow, or too buggy. I can usually write better code myself.