Xilinx Design Calculations for Propagation Delay, Area and Power

[akeedthe]

Hi guys,

Ive designed 5 models of squarers and wish to compare propagation delay, area and power consumption.

For delay, is putting a marker at input and then at stable output and getting the difference the correct way of doing this.
Also, what is maximum combinational delay which is given in the synthesis report.

Area, is number of slices and LUTs used a viable way of calculating this. Theoretically one of my designs is supposed to be more area efficient but shows higher slice/LUT count.
Also, is there anyway fan-in can be used to give an indication of silicon cost/area.

Power consumption is Xpower the only way after synthesis is done? As all my designs are giving me a value of 37mw :-?

Thanking You in advance! :grin:

 

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For delay, is putting a marker at input and then at stable output and getting the difference the correct way of doing this.
Also, what is maximum combinational delay which is given in the synthesis report.

Not sure what you mean by "marker at input". The timing report shows the combinational path delays if that is what you are looking for. If you didn't let the tools add pins then you'll probably have to run trce on the design and query those paths.

Area, is number of slices and LUTs used a viable way of calculating this. Theoretically one of my designs is supposed to be more area efficient but shows higher slice/LUT count.
Also, is there anyway fan-in can be used to give an indication of silicon cost/area.

Utilization of LUTs, registers and memories is what you use. The issue is LUT counts can be inflated by the timing constraints when the design is difficult to meet timing (e.g. replication of registers or replication of logic to reduce fanout).

Power consumption is Xpower the only way after synthesis is done? As all my designs are giving me a value of 37mw :-?

If you want the most accurate power estimate you'll need to run a bunch of functional simulation and import the VCD into Xpower to have realistic power estimates. That is if you've already imported the routed design into Xpower. Also depending on the part you are using, the frequency of any clocks, and the utilization. You may just be seeing the leakage current as that may be the major source of power consumption in the part.

Regards

 

[akeedthe]

I meant by marker was after running the PAR simulation. Is it fine if i use markers at the input and output to calculate the delay in getting a stable output? Or is that not correct for propagation delay?

What exactly is trce and how can i try it out in ISE 10.1 please?

I haven't defined any timing constraints as far as I know.
By any chance would you know if a hierachical CLA vs a normal CLA for the same function were used; which would utilize more slices and LUTs?

I ran Xpower analyzer from the PAR menu under processes. How can I go ahead with this vcd file import please?

Thanking You Immensely!

 

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I meant by marker was after running the PAR simulation. Is it fine if i use markers at the input and output to calculate the delay in getting a stable output? Or is that not correct for propagation delay?

So you must be using ISIM after you've placed and routed the design? Well then you should be able to output the info you need for running Xpower, but I don't know the ISIM commands or menu to do this. I use Modelsim.

What exactly is trce and how can i try it out in ISE 10.1 please?[/qoute]
Under the Tools menu is Timing Analyzer. TRCE is the underlying tool that Timing Analyzer uses to compute the timing. TRCE is the name of the program you can use on the command line.

I haven't defined any timing constraints as far as I know.

Well if you don't have any clocks...do you have any clocks?...then you probably still want some constraints for pin-to-pin delays. You can add those in the constraint manage. Take a look at your timing report it should have a section that shows you the unconstrained paths.

By any chance would you know if a hierachical CLA vs a normal CLA for the same function were used; which would utilize more slices and LUTs?

Assuming you mean a Carry Look Ahead. I haven't designed one of those, since Xilinx 4000 days (no carry chains). With the advent of carry chains in FPGAs I stopped messing around with hand built implementations.

I ran Xpower analyzer from the PAR menu under processes. How can I go ahead with this vcd file import please?

Offhand I can't say. I've looked into doing this but as we normally use pretty conservative estimates of power I've seldom had to improve my estimates beyond importing the PAR results and using a toggle rate of 12.5% for logic and whatever I've determined is the percentage of read and write cycles to memories.

Regards,