Xilinx Core Generator : FIR-compiler

[thoth]

Hi all.
I have newbie question about Xilinx Core Generator: FIR-compiler.

When I start the core ( FIR-compiler ) , and try to customize its parameters, I can change nothing. Just can't select anything except entity name, and provide name of coe file.

I tried do the same in another computers, and had exactly same issue.
I checked on Xilinx site, and found that FIR-compiler is FREE for use.
I have ISE-Webpack installed, so it must work.

Googling not helped, so if anyone could explain me what I do wrong, please.

Best.

 

[Maxwell077]

You may write a top module and instantiate FIR declaration into your top module.
You need to do port mapping and you can give inputs from that top module and can get outputs..

 

[xtcx]

Are you getting any information regarding the completion of the I core generation?...Can u generate the VHDL or Verilog code?...Check in the destination folder if it has generated.If so, just port map with the instance name

 

[thoth]

Hi.

1) I can generate VHDL/Verilog Code.
2) I can't provide during generation process, needed parameters. Just can't change any fields you see in Core-Generator. The only thing I can do, during generation process is typing "next,next,next"

Best.