Xilinx clock generation of values like 15.1 or 30.1MHz and so on

[sherif123]

I have the problem that I need to generate a clock of frequency 20.1 and the no integer relationship between the input crystal clock frequency(ex 27 MHz) and the desired frequency 20.1MHz. Is there a way to generate this using the DCM. The DCM only supports ranges of numbers for multiplication and division.(Xilinx FPGA)
Thanks

 

[TrickyDicky]

can you change the crystal?

 

[sherif123]

I have only two crystals for now, but none of them can solve this problem. I just need to test something, if it's valid a new design will be created with every thing correctly chosen.
I heard that I can cascade two DCMs in series but this will cause higher jitter.

 

[mrflibble]

I heard that I can cascade two DCMs in series but this will cause higher jitter.

And that is exactly right. Can you tell us what the amount of acceptable jitter is for your required 15.1 MHz clock? I'd ask for the phase noise of the oscillator, but usually that's swamped by the fpga added noise anyways.

 

[TrickyDicky]

What is this clock going to be used for? is it internal or external?

 

[sherif123]

I don't know how much jitter I can tolerate (How much is it I can tolerate?). I need to use this clock internally inside the FPGA and will need to interface with external memory.
The external memory is the second problem I face. I can follow the demo example coming with the board with its UCF file to interface with the memory but this is using the external clock oscillator without modifying it with DCM. If I used DCM with the clock, the memory UCF file uses constraints that I can't really understand and don't know how to modify them to work with a clock generated from DCM not from the crystal oscillator at the input pad.
Thanks