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Xilinx 9500 series CPLD PWM code problem

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Mercury

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Hello!
I am a beginner at Xilinx 9500 series CPLDs using Webpack 5.2. I wrote the attached file as a pwm comparator/generator with input latch. The problem is that when I synthesize it I get a warning: found 1 bit latch for signal PWM. Also when I run the fitter report I get a "red X" left of the "fitter report". So I would like to know what I am doing wrong.

Let me expalin a bit more the pwm comparator. In the Cin input I will bring an 8 bit counter output, and at Din the 8 bit pwm value. The concept is as follows:
- the comparator sets pwm output when the Cin reaches top (255).
- The pwm output is cleared when the Din ( or the latched signal data ) equals Cin. This is more or less it.

I thank you in advance for your answer.

Best regards
George Mercury


Sorry, I have tried to attach the file, but I've had no sucess:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Comparator is
Port (
pwm: out std_logic;
str: in std_logic;
rst: in std_logic;

Din: in std_logic_vector(7 downto 0);
Cin: in std_logic_vector(7 downto 0)

);
end Comparator;

architecture comp of Comparator is

signal data: std_logic_vector(7 downto 0);
signal top: std_logic;
signal equ: std_logic;

begin

p00: process(str)
begin
if str'event and str = '1' then
data <= Din;
end if;
end process;


p01: process(top,equ,rst)
begin
if rst = '0' then
pwm <= '0';
elsif top = '1' then
pwm <= '1';
elsif equ = '1' then
pwm <= '0';
end if;
end process;

equ <= '1' when data = Cin else '0';
top <= '1' when Cin = "11111111" else '0';

end comp;
 

Re: CPLD PWM Problem

the code you show is a combinatorial one and latches will be infered for the cases that dos not covered by P01 process. my advice is as follows

1- Take the Clock which the counter count in as an input to your design.
2- Make a process that is activated each rising edge of Clock and compre inside this process the value of Cin and Data directly (i.e if Cin = Data) and according to the reset set or clear the PWM output. by this way you avoid the hazards accosiated with combinational logic and you will avoid infered latches.

regards
 
Re: CPLD PWM Problem

I thank you for your answer. So If I understood right, my mistake was that I did't provide states for the PWM output when non of the if-clauses was true. And as I see it, VHDL used a Latch for the PWM output. Am I right? I will take your advice and use the clock. I thank you again for your fast response.

Geroge
 

Re: CPLD PWM Problem

1- keep in your mind that for any unsepecified case (either in your situation or in the CASE statment ) latches will be iferred to hold the state of the output.

2- When you make the events done on the rising (or falling) with the master clock, this statment is synthesized into DFF's drived by the combinational logic, so the output of combinational logic dos not seen untill the edge of the clock arrived which avoid the following circuit to be affected with the hazards that my appear at the combinational circuit during transitions of its input.
 
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