Xilinx 7.1 synthesis problem

[pankaj]

Hello,

did anybody find a problem with Xilinx CPLD synthesis with its 7.1i version.
I have a design in XC9572XL series. What I have found is that it is synthesising a inverting gate for a buffer. In simulation and the reports everything is fine, but only when the design is downloaded that this anomaly is observed. The same design works fine when synthesised using 6.2 or 6.3 version.

Pankaj

 

[Renjith]

Hi pankaj,
if it has synthesised something wrong, then u will get the wrong results displayed on your post synthesis and place and route simulation.

u can put this problem to xilinx.

 

[Sparc]

If you are getting what you expected as output, this is not an anomaly. Synthesis tools do many opimizations on to achieve the efficient implementation for your functionality. So, the buffer which you might be (mis)interpreting as an inverting logic; either your design is also using the "not" of that logic somewhere in the design OR it might again be corrected by again inverting it back to form the buffer-Reason for this can be: Synthesis tool does it's best to utilize the available resources to it's max. You try out setting different optimization goals and can have a deeper look into the synthesis tool.

 

[priyaphule]

hello pankaj,

have u got the solution for the problem

i am also getting the same problem with xilinux 7.1i version

on test bench waveform i am getting the expected result but after downloading i am getting inverting output for and and nor, not get while for or and nand get it work fine

is there any inverting buffer logic behind it

please send PM to me regardingly

Priya

 

[echo47]

**broken link removed**

 

[kang_computer_01]

so i have problem to can't save testbench waveform can every body help

 

[soccer]

the buffer which you might be (mis)interpreting as an inverting logic; either your design is also using the "not" of that logic somewhere in the design OR it might again be corrected by again inverting it back to form the buffer-Reason for this can be: Synthesis tool does it's best to utilize the available resources to it's max.

 

[MRFGUY]

Actually this topic sould be closed. Because echo47 give the key point for Xilinx 7.1i logic error. I also faced the same problem and follow echo47 link. Finally install service pack3 and all locgic inverting problems are solved.