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xc9572 xilinx - no delay in the output

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bnmbnm

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xc9572 xilinx

please send me,I USE COMMAND OF AFTER 10 NS OR ANY TIME .
AND WRITE MY PROGROM TO IC XC9572,BUT ,IN OUTPUT I CAN NOT SEE ANY DELAY,PLEASE HELP ME.
 

FvM

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xc9572 xilinx

The timed HDL signal assignments are simulation tools only. Their purpose is in simulating the timing behaviour of external hardware and generation of simulation signals. They are ignored (if not causing an error) in synthesis.

To generate timed waveforms with programmable logic, you need a system clock and counters or state machines. Some logic famlies may offer progammable delays in the sub-nanosecond and low nanosecond range. The tools can also utilize routing delays to satisfy timing constraints set for the design.
 

harii74

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Re: xc9572 xilinx

Mr.FVM saying is correct.
"after 10ns" command is not a synthesizeble command.
You can use it in test bench code to generate test input.

To.Mr.FVM
Will you please give me your personal mail ID.i want to discuss more in HDL.
I am from INDIA, TAMILNADU.
 

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