# x/y ratio for matching capacitor

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#### angyp

##### Newbie level 5 if i want to match two caps 4nF and 2.8nF
What X/Y ratio is required to achieve a non-unit size cap ratio
K of 2.8? Assume unit size cap is 6umX6um.
just roughly state out the calculation.

#### borodenkov

##### Full Member level 2 Use unit caps to create your two caps. The unit capacitance can be 0.4nF in your case.

btw, where do you need such huge capacitances???
I would be expect the same numbers in pF...

#### fatbear

##### Junior Member level 3 It's hard to integrated so large caps in IC technology. For the popular technology now, such as 0.18 micron to 0.35 micron CMOS technology, the unit cap value of MIM cap is about 1fF/um^.

#### borodenkov

##### Full Member level 2 For example, in TSMC 0.18u mixed-signal/RF process the maximum MiM capacitor is around 950 fF (30u x 30u) and maximum pmos or nmos cap - around 17 pF

#### angyp

##### Newbie level 5 Oops I am sorry. i am just giving an example.i knew the way of using unit capacitor to get the matching, but i am doubted with the formulas which are given.

the formulas are as below:
for the layout of two capacitors with the ratio being non-integer, given a square capacitor C1 with each side being X to achieve a matched capacitor C2 with a ratio of C2/C1=K, the two dimensions X2 and Y2 of the rectangular capacitor should satisfy the following conditon

K=C2/C1=X1*Y1/X*X (area)

K=C2/C1=X1+Y1/2X (perimeter)
from these two formulas we can obtain the X1,Y1 values by using for good matching of these two capacitors.
what u all think of the above assumption?

#### Humungus

##### Full Member level 6 Just make your unit capacitor of 0.4pF. So, 7 x 0.4 equals 2.8 and 10 x 0.4 equals 4. The use common centroid structure to improve your matching.

##### Full Member level 3 when u use unit capacitor, u don't need care about X and Y (suggestion to use shape of unit capacitor more close to square - this case is more tolerant of process deviations ).

In ur example, may be better to choose 0.2n unit capacitor (or less), because in this case u will get 14 + 20 =34 unit capacitors. Adding another dummy capacitor u will get 5(raw)x7(column)=35 unit capacitors.
Also u need to add another 8x2+5x2=26 dummy unit capacitors around ur main 34 +1 dummy capacitors.

For 0.4n unit capacitor u need to add 6x2+3x2=18 dummy unit capacitors to 14 main + 1 dummy unit capacitors. So u will waste more chip space for dummy capacitors.

#### Sunrising

##### Newbie level 6 Does the dummy capacitor on the edges need to be the same size as the unit capacitor? Can we use the dummy capacitor as minimum size according to the design rule, while keep the space between it and the main capacitors same as that between the other main capacitors?
By the way, for double poly capacitors, shall we pay attention to the space of both poly layers? Or only consider the top layer is enough? (For in most cases, the top layer is smaller than the bottom layer, so the capacitors' value is mainly determined the top layer.)

##### Full Member level 3 It's acceptable to use dummy-edge capacitors size differs from unit capacitor size, because the the same space between capacitors is more important.

Both poly layers space is important because they also have fringe capacitance.

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