How there can be an unknown at the port when ports are given Low or High?
How can x-propgate when ports are given Low or High?
I don't have much experience with gate level simulation, but for shorted outputs I think it will be identical to RTL simulation.Hello std_match
Will the x also be realized in gate level simulation? Is it that in this case of two outputs shorted together, the gate level simulation will also produce 'x' as the RTL simulation produce 'x' ?
There are no shorted outputs in that code. It is only about 'X'-propagation, and it seems to be a case where a difference between RTL simulation and gate level simulation is expected.Then how do the page 9 in attached paper talk about simulation and synthesis mismatch for casex and casez?