X and Z Propagation in Design

[kunal1514]

Hi All,

Can any body explain at What conditions X and Z propagates in design.

 

[jeet_asic]

which design? can't see any image .

 

[ljxpjpjljx]

usually we will debug X in gate level simulation! which part do you want to know?

 

[kunal1514]

Suppose in waveform I am seeing X and Z propagating for a particular signal.

What should be my approach towards debugging for the X and Z propagation.

---------- Post added at 17:13 ---------- Previous post was at 17:12 ----------

means X or Z propagation

 

[sushil.ece]

X progagation comes from the contention in the simulation means teh same net is being driven from the two sources .I am not sure which tools You are using .If you are using Debussy then you can easiy trace the netlist by loading your design .
If it is Post synthesized netlist then X can come from the Due to the Timing Violation at the flop then you need to Identify the source flop by backtracing the netlist .

"Z" propagation is due to open wires .You have to back trace even in this case also

 

[kunal1514]

I think we are missing one more reason for the (X) propagation in designs, which is (SET-UP) and (HOLD) violation. I was reading an article which mentions cause of (X) propagation while doing (GLS - Gate Level Simulation) is timing violations.

---------- Post added at 14:27 ---------- Previous post was at 14:26 ----------

Please provide additional details or papers to support the above mentioned comments