writing the test bench in verilog

[anusha vasanta]

Hi all,
can anyone suggest me the best way of writing test bench for verifying all of the corner cases.
you can put any link or some small gist regarding it. thanx in advance

 

[sharath666]

Writing testbench is one thing, verifying all corner cases is another thing.
If you want to write a testbench, you should be able to get info from websites like testbench.in or some others.
If you want to verify all corner cases, see to it that you understand clearly what you are doing, identify all possible kind of input scenarios. Once you identify all possible scenarios,translating them to verilog/VHDL should not be tough.