I am new to SDC constraints,
in synchronous clock definition
If A is input port and B is output pin then we can define create_clock on A and generated_clock on B with divide_by option.
Now say X is input and Y is output, and both are asynchronous with each other.
Where such scenario will come in design and how to write SDC constraints on input and output?
The generated clock has to be dependent of the source clock , else the other possibility is when one of the flops has a clock that is generated using combinatorial logic of some other input pins , then you might have a scenario of Asynchronous clocks; But that kind of design is never encouraged and to fix timing on such flops is a nightmare.