kaisopos
Newbie level 4
hi all,
I am using the command write_spice_deck of primetime because I want to simulate a path of my design in spice:
write_spice_deck -output <spice_file> -sub_circuit_file <extracted_netlist> $timing_path
however, primetime complaints for the format of my extracted netlist:
Warning: SPICE pin 'BULK!'/'VSS'/'VDD' for cell 'xxx' is not in the library. (DES-039)
My extracted netlist has many subckts that look like this:
--------------------------
.subckt NAME C VSS VDD B A Y bulk!
*
* bulk! bulk!
* Y Y
* A A
* B B
* VDD VDD
* VSS VSS
* C C
(nodes, parasitic capacitances, etc....)
--------------------------
I assume that if I add the PININFO for these pins ('BULK!'/'VSS'/'VDD') the problem will get resolved, so I add this line right below the .subckt line:
*.PININFO C:I VSS:B VDD:B B:I A:I Y:O
..and now I get another warning:
Warning: No SPICE pin order info for cell type 'xxx'. (DES-037)
anyone is familiar with this warning and can tell me what I did wrong?
thanks a bunch!
I am using the command write_spice_deck of primetime because I want to simulate a path of my design in spice:
write_spice_deck -output <spice_file> -sub_circuit_file <extracted_netlist> $timing_path
however, primetime complaints for the format of my extracted netlist:
Warning: SPICE pin 'BULK!'/'VSS'/'VDD' for cell 'xxx' is not in the library. (DES-039)
My extracted netlist has many subckts that look like this:
--------------------------
.subckt NAME C VSS VDD B A Y bulk!
*
* bulk! bulk!
* Y Y
* A A
* B B
* VDD VDD
* VSS VSS
* C C
(nodes, parasitic capacitances, etc....)
--------------------------
I assume that if I add the PININFO for these pins ('BULK!'/'VSS'/'VDD') the problem will get resolved, so I add this line right below the .subckt line:
*.PININFO C:I VSS:B VDD:B B:I A:I Y:O
..and now I get another warning:
Warning: No SPICE pin order info for cell type 'xxx'. (DES-037)
anyone is familiar with this warning and can tell me what I did wrong?
thanks a bunch!