# Write Failure Probability in STTMRAM

#### unix_amr

##### Newbie level 4
Dear all,

I am trying to calculate and simulate "Write Failure Probability" of an STT-MRAM cell by HSPICE (and MATLAB). I know that I must use Monte-Carlo simulations in HSPICE, but I have no idea how to use Monte-Carlo results for measuring write failure probability. I would be so grateful if you would help me on how to do this.

Thanks

##### Super Moderator
Staff member
Do you wish to:
* build a list of causes of write failure in IC's, and then simulate those causes randomly

or

* do you wish to do various test runs, then subject the results to contrast and comparison?

#### unix_amr

##### Newbie level 4
Do you wish to:
* build a list of causes of write failure in IC's, and then simulate those causes randomly

or

* do you wish to do various test runs, then subject the results to contrast and comparison?
Thanks for your reply. part 1 is my goal. (building a list of causes of write failure...)

#### dick_freebird

To gauge probability you need to get the write cycle
statistics. Or make some up. That's going to be tough,
the only publications are probably early-stage tech
development / "look, we did it!" papers and by the
time a product is qualified for production there will
be / had better have been significant progress in
defect and variability reduction.

Nohow would you expect to find details of write cycle
vs programming pulse distributions, that's key
competitive info.

But maybe you can find a paper that has some kind
of statistics, to hang a thesis on.

##### Super Moderator
Staff member
I imagine that research teams encountered lots of write errors, while they tried to track down anomalies that cause them, then construct workarounds (example, routines to verify that reads and writes are correct). Somewhere there ought to be a few real-life stories.

Thinking about typical electronic problems in any fast-acting circuit...
* There might be glitches on internal power lines due to switching between banks of memory, etc.
* Accidental interactions during a refresh routine, etc.
* Magnetic and inductive interference from nearby devices, speakers, hard-drives, etc.

Another possibility: cosmic rays have been speculated to be an occasional cause of glitches in micro-circuitry. It's the sort of thing that's hard to verify if or when it happens. It can't absolutely be ruled out.

#### unix_amr

##### Newbie level 4
Ok. I know the causes of write errors in STTMRAM, but I do not know how to use variance and mean to plot failure probability as an attached FIg.
Thanks

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